EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 139

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II GX Devices
Arria II GX I/O Structure
Table 6–3. Arria II GX Pin Migration Across Densities
Arria II GX I/O Structure
© July 2010 Altera Corporation
358-pin
Flip Chip
UBGA
572-pin
Flip Chip
FBGA
780-pin
Flip Chip
FBGA
1152-pin
Flip Chip
FBGA
Note to
(1) Each transceiver channel consists of two TX pins, two RX pins and a transceiver clock pin.
Package
Table
6–3:
I/O
Clock
XCVR
channel
I/O
Clock
XCVR
channel
I/O
Clock
XCVR
channel
I/O
Clock
XCVR
channel
Pin Type
The IOE in Arria II GX devices contains a bidirectional I/O buffer and I/O registers to
support a completely embedded bidirectional single data rate (SDR) or double data
rate (DDR) transfer. The IOEs are located in I/O blocks around the periphery of the
Arria II GX device. There are up to four IOEs per row I/O block and four IOEs per
column I/O block.
The Arria II GX bidirectional IOE supports these features:
■
■
■
■
■
■
■
■
■
EP2AGX45
Programmable input delay
Programmable output current strength
Programmable slew rate
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
R
R
PCI clamping diode
S
D
144
240
352
12
12
12
—
—
—
OCT with or without calibration
OCT
4
8
8
EP2AGX65
144
240
352
12
12
12
—
—
—
4
8
8
EP2AGX95
248
360
440
—
—
—
12
12
12
12
12
8
Device
EP2AGX125 EP2AGX190 EP2AGX260
248
360
440
—
—
—
12
12
12
12
12
8
360
600
—
—
—
—
—
—
12
12
12
16
Arria II GX Device Handbook, Volume 1
360
600
—
—
—
—
—
—
12
12
12
16
6–5