EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 97

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Clock Networks in Arria II GX Devices
Clock Network Sources
© July 2010
Altera Corporation
1
In Arria II GX devices, clock input pins, internal logic, transceiver clocks, and PLL
outputs can drive the GCLK and RCLK networks. For the connectivity between
dedicated CLK[4..15] pins and the GCLK and RCLK networks, refer to
and
Dedicated Clock Inputs Pins
The CLK pins can either be differential clocks or single-ended clocks. Arria II GX
devices support 6 differential clock inputs or 12 single-ended clock inputs. You can
also use the dedicated clock input pins CLK[4..15] for high fan-out control signals
such as asynchronous clears, presets, and clock enables for protocol signals such as
TRDY and IRDY for PCI Express
Logic Array Blocks
You can drive up to four signals into each GCLK and RCLK network with logic array
block (LAB)-routing to allow internal logic to drive a high fan-out, low-skew signal.
You cannot drive Arria II GX PLLs by internally generated GCLKs or RCLKs. The
input clock to the PLL has to come from dedicated clock input pins or PLL-fed
GCLKs/RCLKs only.
PLL Clock Outputs
Arria II GX PLLs can drive both GCLK and RCLK networks, as shown in
and
Table 5–2
Table 5–2. Clock Input Pin Connectivity to GCLK Networks
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
Note to
(1) GCLK[0..3] is not driven by any clock pins because there are no dedicated clock pins on the left side of the
Clock Resources
Table
Table
Arria II GX device.
Table
lists the connection between the dedicated clock input pins and GCLKs.
5–3.
5–6.
5–2:
(1)
—
—
—
v
4
—
—
—
v
5
—
—
—
v
®
6
(PCIe
—
—
—
v
7
®
) through GCLK or RCLK networks.
—
—
—
v
8
CLK (Pins)
—
—
—
v
9
10
—
—
—
v
Arria II GX Device Handbook, Volume 1
11
—
—
—
v
12
—
—
—
v
13
—
—
—
v
Table 5–5
Table 5–2
14
—
—
—
v
15
—
—
—
v
5–5