EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 39

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
Document Revision History
ALM Interconnects
Clear and Preset Logic Control
Document Revision History
Table 2–1. Document Revision History
© June 2009 Altera Corporation
June 2009, v1.1
February 2009, v1.0
Date and Document
Version
There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and
Shared Arithmetic chain. Arria II GX devices include an enhanced interconnect
structure in LABs for routing shared arithmetic chains and carry chains for efficient
arithmetic functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect.
shows the shared arithmetic chain, carry chain, and register chain interconnects.
Figure 2–13. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
The ALM directly supports an asynchronous clear function. You can achieve the
register preset through the Quartus II software’s NOT-gate push-back logic option.
Each LAB supports up to two clears.
Arria II GX devices provide a device-wide reset pin (DEV_CLRn) that resets all
registers in the device. An option set before compilation in the Quartus II software
enables this pin. This device-wide reset overrides all other control signals.
Table 2–1
Updated
Initial Release.
shows the revision history for this document.
Figure
routing to adjacent ALM
2–6.
Carry chain & shared
arithmetic chain
interconnect
Changes Made
Local
Local interconnect
routing among ALMs
in the LAB
ALM 10
ALM 1
ALM 2
ALM 3
Register chain
routing to adjacent
ALM's register input
Arria II GX Device Handbook, Volume 1
Summary of Changes
Figure 2–13
—
—
2–13