R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet
R5F213J6CNNP#U0
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R5F213J6CNNP#U0 Summary of contents
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R8C/3JC Group 16 RENESAS MCU R8C Family / R8C/3x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) Address XXXXh Bit b7 b6 Symbol XXX7 XXX6 After Reset 0 0 Bit Symbol b0 XXX0 XXX bit b1 XXX1 b2 — ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. Asynchronous Communication Interface ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Features ..................................................................................................................................................... 1 1.1.1 Applications .......................................................................................................................................... 1 1.1.2 Specifications ........................................................................................................................................ 2 1.2 Product List ............................................................................................................................................... 4 1.3 Block Diagram .......................................................................................................................................... 5 1.4 Pin Assignment .......................................................................................................................................... 6 1.5 Pin ...
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Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 37 5.8 Reset Source Determination Function ..................................................................................................... 37 6. Voltage Detection Circuit .............................................................................................................. 38 6.1 Overview ................................................................................................................................................. 38 6.2 Registers .................................................................................................................................................. 42 6.2.1 Voltage Monitor Circuit Control Register (CMPA) ........................................................................... 42 6.2.2 Voltage ...
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Input Threshold Control Register 0 (VLT0) ....................................................................................... 83 7.4.23 Input Threshold Control Register 1 (VLT1) ....................................................................................... 83 7.5 Port Settings ............................................................................................................................................ 84 7.6 Unassigned Pin Handling ...................................................................................................................... 102 8. Bus .............................................................................................................................................. 103 9. Clock Generation Circuit ............................................................................................................. 105 9.1 ...
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Wait Mode ........................................................................................................................................ 137 9.9.3 Oscillation Stop Detection Function ................................................................................................. 138 9.9.4 Oscillation Circuit Constants ............................................................................................................ 138 10. Protection .................................................................................................................................... 139 10.1 Register .................................................................................................................................................. 139 10.1.1 Protect Register (PRCR) ................................................................................................................... 139 11. Interrupts ..................................................................................................................................... 140 11.1 Overview ............................................................................................................................................... 140 ...
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External Interrupt and Key Input Interrupt ....................................................................................... 165 11.8.4 Changing Interrupt Sources .............................................................................................................. 166 11.8.5 Rewriting Interrupt Control Register ................................................................................................ 167 12. ID Code Areas ............................................................................................................................ 168 12.1 Overview ............................................................................................................................................... 168 12.2 Functions ............................................................................................................................................... 169 12.3 Forced Erase Function ...
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Control Data Allocation and DTC Vector Table .............................................................................. 193 15.3.4 Normal Mode .................................................................................................................................... 198 15.3.5 Repeat Mode ..................................................................................................................................... 199 15.3.6 Chain Transfers ................................................................................................................................. 200 15.3.7 Interrupt Sources ............................................................................................................................... 200 15.3.8 Operation Timings ............................................................................................................................ 201 15.3.9 Number of DTC Execution ...
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Timer RB Primary Register (TRBPR) .............................................................................................. 229 18.2.8 Timer RB/RC Pin Select Register (TRBRCSR) ............................................................................... 229 18.3 Timer Mode ........................................................................................................................................... 230 18.3.1 Timer RB I/O Control Register (TRBIOC) in Timer Mode ............................................................. 230 18.3.2 Timer Write Control during Count ...
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Timer Mode (Output Compare Function) ............................................................................................. 269 19.5.1 Timer RC Control Register 1 (TRCCR1) for Output Compare Function ........................................ 271 19.5.2 Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function ................................ 272 19.5.3 Timer RC I/O Control ...
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Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi Input Capture Function ............................................................................................... 314 20.3.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 315 20.3.16 Timer RD Pin Select ...
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Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 349 20.5.18 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 349 20.5.19 Operating Example ........................................................................................................................... 350 20.5.20 A/D Trigger Generation .................................................................................................................... 352 20.6 Reset Synchronous PWM Mode ........................................................................................................... 353 20.6.1 Module ...
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Timer RD Mode Register (TRDMR) in PWM3 Mode ..................................................................... 388 20.8.6 Timer RD Function Control Register (TRDFCR) in PWM3 Mode ................................................. 389 20.8.7 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM3 Mode .................................... 390 20.8.8 Timer RD ...
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Serial Interface (UARTi ( 1)) ............................................................................................ 425 22.1 Overview ............................................................................................................................................... 425 22.2 Registers ................................................................................................................................................ 427 22.2.1 UARTi Transmit/Receive Mode Register (UiMR ........................................................ 427 22.2.2 UARTi Bit Rate Register (UiBRG ...
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Serial Data Logic Switching Function .............................................................................................. 471 23.4.5 TXD and RXD I/O Polarity Inverse Function .................................................................................. 471 23.4.6 CTS/RTS Function ............................................................................................................................ 472 23.4.7 RXD2 Digital Filter Select Function ................................................................................................ 472 2 23.5 Special Mode Mode) .................................................................................................................. ...
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Data Reception .................................................................................................................................. 519 25.5.4 SCS Pin Control and Arbitration ...................................................................................................... 521 25.6 Notes on Synchronous Serial Communication Unit .............................................................................. 522 2 26 bus Interface ......................................................................................................................... 523 26.1 Overview ............................................................................................................................................... 523 26.2 Registers ................................................................................................................................................ 526 26.2.1 Module ...
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Hardware LIN End Processing ......................................................................................................... 572 27.5 Interrupt Requests .................................................................................................................................. 573 27.6 Notes on Hardware LIN ........................................................................................................................ 574 28. A/D Converter ............................................................................................................................. 575 28.1 Overview ............................................................................................................................................... 575 28.2 Registers ................................................................................................................................................ 577 28.2.1 On-Chip Reference Voltage Control Register (OCVREFCR) ......................................................... ...
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ID Code Check Function .................................................................................................................. 611 31.3.2 ROM Code Protect Function ............................................................................................................ 612 31.3.3 Option Function Select Register (OFS) ............................................................................................ 612 31.4 CPU Rewrite Mode ............................................................................................................................... 613 31.4.1 Flash Memory Status Register (FST) ............................................................................................... 614 31.4.2 Flash Memory Control ...
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External Interrupt and Key Input Interrupt ....................................................................................... 681 34.2.4 Changing Interrupt Sources .............................................................................................................. 682 34.2.5 Rewriting Interrupt Control Register ................................................................................................ 683 34.3 Notes on ID Code Areas ........................................................................................................................ 684 34.3.1 Setting Example of ID Code Areas ................................................................................................... 684 34.4 ...
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CPU Rewrite Mode ........................................................................................................................... 703 34.18 Notes on Noise ...................................................................................................................................... 707 34.18.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up ............................................................................................................................................ 707 34.18.2 Countermeasures against Noise Error of Port Control Registers ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Module Standby Control Register 0009h System Clock Control ...
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Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch DTC ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register ...
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Address Register 0160h UART1 Transmit/Receive Mode Register 0161h UART1 Bit Rate Register 0162h UART1 Transmit Buffer Register 0163h 0164h UART1 Transmit/Receive Control Register 0 0165h UART1 Transmit/Receive Control Register 1 0166h UART1 Receive Buffer Register 0167h 0168h 0169h 016Ah 016Bh ...
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Address Register 01E0h Pull-Up Control Register 0 01E1h Pull-Up Control Register 1 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register 01F1h Port P2 Drive Capacity Control Register ...
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Address Register 2C90h DTC Control Data 10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC ...
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R8C/3JC Group RENESAS MCU 1. Overview 1.1 Features The R8C/3JC Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing ...
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R8C/3JC Group 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/3JC Group. Table 1.1 Specifications for R8C/3JC Group (1) Item Function CPU Central processing unit Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O ...
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R8C/3JC Group Table 1.2 Specifications for R8C/3JC Group (2) Item Function Serial UART0, UART1 Interface UART2 Synchronous Serial Communication Unit (SSU bus LIN Module A/D Converter D/A Converter Comparator B Flash Memory Operating Frequency/Supply Voltage Current consumption ...
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R8C/3JC Group 1.2 Product List Table 1.3 lists Product List for R8C/3JC Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/3JC Group. Table 1.3 Product List for R8C/3JC Group Part No. Program ROM R5F213J2CNNP 8 ...
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R8C/3JC Group 1.3 Block Diagram Figure 1.2 shows a Block Diagram. 6 I/O ports Port P0 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 ...
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R8C/3JC Group 1.4 Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Tables 1.4 and 1.5 outline the Pin Name Information by Pin Number. P1_0/AN8/KI0(/TRCIOD) P0_7/AN0/DA1(/TRCIOC) P0_6/AN1/DA0(/TRCIOD) P0_4/AN3/TREO(/TRCIOB) P0_3/AN4(/CLK1/TRCIOB) P0_2/AN5(/RXD1/TRCIOA/TRCTRG) P0_1/AN6(/TXD1/TRCIOA/TRCTRG) P4_2/VREF MODE Notes: 1. Can be assigned to the ...
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R8C/3JC Group Table 1.4 Pin Name Information by Pin Number (1) Pin Control Pin Port Number 1 (XCIN) P4_3 2 (XCOUT) P4_4 3 RESET 4 XOUT P4_7 5 VSS/AVSS 6 XIN P4_6 7 VCC/AVCC 8 P3_7 9 P3_5 10 P3_4 ...
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R8C/3JC Group Table 1.5 Pin Name Information by Pin Number (2) Pin Control Pin Port Number 31 P0_4 32 P0_3 33 P0_2 34 P0_1 35 P4_2 36 MODE Note: 1. Can be assigned to the pin in parentheses by a ...
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R8C/3JC Group 1.5 Pin Functions Tables 1.6 and 1.7 list Pin Functions. Table 1.6 Pin Functions (1) Item Pin Name Power supply input VCC, VSS Analog power AVCC, AVSS supply input Reset input RESET MODE MODE XIN clock input XIN ...
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R8C/3JC Group Table 1.7 Pin Functions (2) Item Pin Name Reference voltage VREF input A/D converter AN0 to AN1, AN3 to AN6, AN8 to AN11 ADTRG D/A converter DA0, DA1 Comparator B IVCMP1, IVCMP3 IVREF1, IVREF3 I/O port P0_1 to ...
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R8C/3JC Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 R2 R3 ...
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R8C/3JC Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) ...
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R8C/3JC Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set ...
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R8C/3JC Group 3. Memory 3.1 R8C/3JC Group Figure 3 Memory Map of R8C/3JC Group. The R8C/3JC Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with ...
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R8C/3JC Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.13 lists the ID Code Areas and Option Function Select ...
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R8C/3JC Group Table 4.2 SFR Information (2) Address 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h ...
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R8C/3JC Group Table 4.3 SFR Information (3) Address 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC ...
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R8C/3JC Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D ...
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R8C/3JC Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN ...
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R8C/3JC Group Table 4.6 SFR Information (6) Address 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt Enable Register ...
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R8C/3JC Group Table 4.7 SFR Information (7) Address 0180h Timer RA Pin Select Register 0181h Timer RB/RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h Timer RD Pin Select Register ...
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R8C/3JC Group Table 4.8 SFR Information (8) Address 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h ...
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R8C/3JC Group Table 4.9 SFR Information (9) Address 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC ...
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R8C/3JC Group Table 4.10 SFR Information (10) Address 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h ...
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R8C/3JC Group Table 4.11 SFR Information (11) Address 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h ...
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R8C/3JC Group Table 4.12 SFR Information (12) Address 2CF0h DTC Control Data 22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h : 2FFFh X: Undefined Note: 1. The ...
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R8C/3JC Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows a Block Diagram of Reset Circuit. ...
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R8C/3JC Group Table 5.2 lists the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence. Table 5.2 Pin Functions while RESET Pin Level is “L” Pin ...
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R8C/3JC Group 5.1 Registers 5.1.1 Processor Mode Register 0 (PM0) Address 0004h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 — b3 PM03 Software reset bit b4 — Nothing ...
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R8C/3JC Group 5.1.3 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...
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R8C/3JC Group 5.1.4 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — After Reset Bit Symbol b0 WDTUFS0 Watchdog timer underflow period set bit b1 WDTUFS1 b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 WDTRCS1 ...
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R8C/3JC Group 5.2 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer ...
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R8C/3JC Group VCC RESET Figure 5.4 Example of Hardware Reset Circuit and Operation RESET Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation REJ09B0602-0100 Rev.1.00 May 12, 2010 1.8 V VCC 0 ...
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R8C/3JC Group 5.3 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, ...
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R8C/3JC Group 5.4 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. To use voltage ...
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R8C/3JC Group 5.5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning ...
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R8C/3JC Group 5.7 Cold Start-Up/Warm Start-Up Determination Function The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during ...
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R8C/3JC Group 6. Voltage Detection Circuit The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. 6.1 Overview The detection voltage of voltage detection ...
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R8C/3JC Group VCC Level Selection Circuit (4 levels) VDSEL1 to VDSEL0 Level Selection Circuit (16 levels) VD1S3 to VD1S0 Figure 6.1 Voltage Detection Circuit Block Diagram REJ09B0602-0100 Rev.1.00 May 12, 2010 VCA25 + - ≥ Vdet0 VCA26 + - ≥ ...
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R8C/3JC Group Voltage detection 0 circuit Level selection VCC VDSEL1 to VDSEL0 VW0C0: Bit in VW0C register VCA25: Bit in VCA2 register VDSEL0, VDSEL1: Bits in OFS register Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit Voltage ...
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R8C/3JC Group Voltage detection 2 circuit fOCO-S VCA27 Level VCA13 VCC change + Voltage - detection 2 signal Internal reference voltage When VCA27 bit is set to 0 (disabled), voltage detection 2 signal is driven high. Watchdog timer block Watchdog ...
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R8C/3JC Group 6.2 Registers 6.2.1 Voltage Monitor Circuit Control Register (CMPA) Address 0030h Bit b7 b6 Symbol COMPSEL — After Reset 0 Bit Symbol b0 — Reserved bits b1 — b2 — b3 — b4 IRQ1SEL Voltage monitor 1 interrupt ...
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R8C/3JC Group 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) Address 0031h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. ...
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R8C/3JC Group 6.2.4 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset 0 0 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 0 0 The ...
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R8C/3JC Group 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) Address 0036h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 VD1S0 Voltage detection 1 level select bit (Reference voltage when the voltage falls) b1 VD1S1 ...
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R8C/3JC Group 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) Address 0038h Bit b7 b6 Symbol — — After Reset 1 1 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 1 ...
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R8C/3JC Group 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) Address 0039h Bit b7 b6 Symbol VW1C7 — After Reset 1 0 Bit Symbol b0 VW1C0 Voltage monitor 1 interrupt enable bit b1 VW1C1 Voltage monitor 1 digital filter disable ...
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R8C/3JC Group 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) Address 003Ah Bit b7 b6 Symbol VW2C7 — After Reset 1 0 Bit Symbol b0 VW2C0 Voltage monitor 2 interrupt enable bit b1 VW2C1 Voltage monitor 2 digital filter disable ...
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R8C/3JC Group 6.2.9 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...
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R8C/3JC Group 6.3 VCC Input Voltage 6.3.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.3.2 Monitoring Vdet1 Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register ...
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R8C/3JC Group 6.4 Voltage Monitor 0 Reset To use voltage monitor 0 reset, set the LVDAS bit in the OFS register to 0 (voltage monitor 0 reset enabled after reset). Figure 6.5 shows an Operating Example of Voltage Monitor 0 ...
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R8C/3JC Group 6.5 Voltage Monitor 1 Interrupt Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of Voltage Monitor 1 Interrupt. To use the voltage monitor 1 interrupt to ...
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R8C/3JC Group Vdet1 1.8 V (1) VW1C3 bit VW1C2 bit VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital ...
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R8C/3JC Group 6.6 Voltage Monitor 2 Interrupt Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of Voltage Monitor 2 Interrupt. To use the voltage monitor 2 interrupt to ...
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R8C/3JC Group Vdet2 (1) 1.8 V VCA13 bit VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital ...
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R8C/3JC Group 7. I/O Ports There are 31 I/O ports P0_1 to P0_4, P0_6, P0_7, P1, P2_0 to P2_5, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, and P6_6 (P4_3 and P4_4 can be used as I/O ports if the ...
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R8C/3JC Group 7.1 Functions of I/O Ports The PDi_j ( bit in the PDi ( register controls I/O of the ports P0_1 to P0_4, P0_6, P0_7, P1, P2_0 to P2_5, P3_1, ...
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R8C/3JC Group P0_1 to P0_4 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of A/D converter P0_6 and P0_7 Direction register Output from individual peripheral function ...
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R8C/3JC Group P1_3 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Analog input of A/D converter Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each ...
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R8C/3JC Group P1_4 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function P1_5 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input ...
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R8C/3JC Group P1_6 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Analog input of comparator B P1_7 Direction register Output from individual peripheral function enabled Data bus Port ...
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R8C/3JC Group P2_0 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Input to external interrupt P2_1 to P2_5 Direction register Output from individual peripheral function enabled Data bus ...
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R8C/3JC Group P3_1 Direction register Output from individual peripheral function enabled Data bus Port latch P3_3 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of comparator ...
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R8C/3JC Group P3_4 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of comparator B P3_5 Direction register Output from individual peripheral function enabled Port latch Data ...
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R8C/3JC Group P3_7 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. ...
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R8C/3JC Group P4_2/VREF Data bus P4_3/XCIN Pull-up selection Direction register Data bus Port latch P4_4/XCOUT Pull-up selection Direction register Port latch Data bus Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. ...
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R8C/3JC Group P4_5 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Input to external interrupt A/D trigger input Note: 1. symbolizes a parasitic diode. Ensure the input voltage ...
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R8C/3JC Group P4_6/XIN Pull-up selection Direction register Data bus Port latch P4_7/XOUT Pull-up selection Direction register Data bus Port latch Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. CM05: Bit in ...
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R8C/3JC Group P6_6 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Input to external interrupt Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port ...
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R8C/3JC Group 7.4 Registers 7.4.1 Port Pi Direction Register (PDi Address 00E2h (PD0 (1) ), 00E3h (PD1), 00E6h (PD2 Bit b7 b6 Symbol PDi_7 PDi_6 After Reset 0 0 Bit Symbol b0 PDi_0 Port ...
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R8C/3JC Group 7.4.2 Port Pi Register (Pi Address 00E0h (P0 (1) ), 00E1h (P1), 00E4h (P2 Bit b7 b6 Symbol Pi_7 Pi_6 After Reset X X Bit Symbol b0 Pi_0 Port Pi_0 bit b1 ...
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R8C/3JC Group 7.4.3 Timer RA Pin Select Register (TRASR) Address 0180h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TRAIOSEL0 TRAIO pin select bit b1 TRAIOSEL1 b2 — Reserved bits b3 — b4 — b5 ...
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R8C/3JC Group 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Bit b7 b6 Symbol — TRCIOBSEL2 TRCIOBSEL1 TRCIOBSEL0 After Reset 0 0 Bit Symbol b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit b1 TRCIOASEL1 b2 TRCIOASEL2 b3 — Nothing is ...
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R8C/3JC Group 7.4.7 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit b7 b6 Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 After Reset 0 0 Bit Symbol b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 — Nothing is assigned. If ...
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R8C/3JC Group 7.4.9 UART0 Pin Select Register (U0SR) Address 0188h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD0SEL0 TXD0 pin select bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...
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R8C/3JC Group 7.4.11 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 TXD2SEL1 b2 TXD2SEL2 b3 — Nothing is assigned. If necessary, ...
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R8C/3JC Group 7.4.13 SSU/IIC Pin Select Register (SSUIICSR) Address 018Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 IICSEL 2 SSU/I C bus switch bit b1 — Reserved bit b2 — Nothing is assigned. If ...
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R8C/3JC Group 7.4.15 I/O Function Pin Select Register (PINSR) Address 018Fh Bit b7 b6 Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL After Reset 0 0 Bit Symbol b0 XCSEL XCIN/XCOUT pin connect bit b1 — Reserved bit b2 — Nothing is ...
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R8C/3JC Group 7.4.16 Pull-Up Control Register 0 (PUR0) Address 01E0h Bit b7 b6 Symbol PU07 PU06 After Reset 0 0 Bit Symbol b0 PU00 P0_1 to P0_3 pull-up b1 PU01 P0_4, P0_6, and P0_7 pull-up b2 PU02 P1_0 to P1_3 ...
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R8C/3JC Group 7.4.18 Port P1 Drive Capacity Control Register (P1DRR) Address 01F0h Bit b7 b6 Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0 After Reset 0 0 Bit Symbol b0 P1DRR0 P1_0 drive capacity b1 P1DRR1 P1_1 drive capacity ...
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R8C/3JC Group 7.4.20 Drive Capacity Control Register 0 (DRR0) Address 01F2h Bit b7 b6 Symbol DRR07 DRR06 After Reset 0 0 Bit Symbol b0 DRR00 P0_1 to P0_3 drive capacity b1 DRR01 P0_4, P0_6, and P0_7 drive capacity b2 — ...
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R8C/3JC Group 7.4.21 Drive Capacity Control Register 1 (DRR1) Address 01F3h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 DRR10 P4_3 drive capacity b1 DRR11 P4_4 to P4_7 drive capacity b2 — Nothing is assigned. ...
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R8C/3JC Group 7.4.22 Input Threshold Control Register 0 (VLT0) Address 01F5h Bit b7 b6 Symbol VLT07 VLT06 After Reset 0 0 Bit Symbol b0 VLT00 P0_1 to P0_4, P0_6, and P0_7 input level select bit b1 VLT01 b2 VLT02 P1 ...
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R8C/3JC Group 7.5 Port Settings Tables 7.5 to 7.49 list the port settings. Table 7.5 Port P0_1/AN6/TXD1/TRCIOA/TRCTRG Register PD0 ADINSEL CH ADGSEL TXD1SEL Bit PD0_1 ...
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R8C/3JC Group Table 7.7 Port P0_3/AN4/CLK1/TRCIOB Register PD0 ADINSEL CH ADGSEL CLK1SEL SMD Bit PD0_3 Setting ...
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R8C/3JC Group Table 7.9 Port P0_6/AN1/DA0/TRCIOD Register PD0 ADINSEL CH Bit PD0_6 Setting Value ...
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R8C/3JC Group Table 7.12 Port P1_1/KI1/AN9/TRCIOA/TRCTRG Register PD1 KIEN CH Bit PD1_1 KI1EN Setting Value Notes: 1. ...
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R8C/3JC Group Table 7.14 Port P1_3/KI3/AN11/TRCIOC Register PD1 KIEN ADINSEL CH Bit PD1_3 KI3EN Setting Value ...
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R8C/3JC Group Table 7.16 Port P1_5/RXD0/TRAIO/INT1 Register PD1 U0SR Bit PD1_5 RXD0SEL0 0 X Other than 10b 1 X Other than 10b 0 1 Other than 10b Other than 10b Setting 0 X Value X X ...
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R8C/3JC Group Table 7.19 Port P2_0/TRDIOA0/TRDCLK/INT1/TRCIOB Register PD2 TRDPSR0 Bit PD2_0 TRDIOA0SEL0 Setting Value Notes: 1. Pulled up by setting the PU04 ...
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R8C/3JC Group Table 7.21 Port P2_2/TRDIOB0/TRCIOD Register PD2 TRDPSR0 TRDIOB0SEL Bit PD2_2 1 0 Other than 10b 1 Other than 10b 0 1 Setting X 1 Value Notes: 1. Pulled up by ...
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R8C/3JC Group Table 7.25 Port P3_1/TRBO Register PD3 TRBRCSR Bit PD3_1 TRBOSEL0 0 0 Setting 1 0 Value Notes: 1. Pulled up by setting the PU06 bit in the PUR0 register ...
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R8C/3JC Group Table 7.27 Port P3_4/TRCIOC/TRDIOC1/SSI/RXD2/SCL2/TXD2/SDA2/IVREF3 Synchronous Serial Communication Unit (Refer to Table 25.4 Register PD3 SSUIICSR Association between Communication Modes and I/O Pins .) SSI Bit PD3_4 IICSEL output control ...
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R8C/3JC Group Table 7.28 Port P3_5/SCL/SSCK/TRCIOD/TRDIOD1/CLK2 Register PD3 SSUIICSR ICCR1 Communication Bit PD3_5 IICSEL ICE ...
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R8C/3JC Group Table 7.29 Port P3_7/SSO/TXD2/SDA2/RXD2/SCL2/TRAO/SDA Register PD3 SSUIICSR ICCR1 Bit PD3_7 IICSEL ICE Setting 0 Value ...
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R8C/3JC Group Table 7.31 Port P4_3/XCIN Register PD4 PINSR CM0 Bit PD4_3 XCSEL CM03 CM04 CM10 CM12 Setting 0 Value Notes: 1. ...
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R8C/3JC Group Table 7.33 Port P4_5/INT0/RXD2/SCL2/ADTRG Register PD4 INTEN Bit PD4_5 INT0EN Setting Value Notes: 1. Pulled up by setting the PU11 bit in ...
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R8C/3JC Group Table 7.35 Port P4_7/XOUT Register PD4 PINSR Bit PD4_7 XCSEL CM03 CM04 CM05 CM10 CM11 CM12 CM13 Setting Value Notes: 1. Pulled up ...
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R8C/3JC Group Table 7.37 TRBO Pin Setting Register TRBIOC Bit TOCNT TMOD1 0 0 Setting value 0 1 Table 7.38 TRCIOA Pin Setting Register TRCOER TRCMR Bit EA PWM2 Setting 1 Value ...
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R8C/3JC Group Table 7.42 TRDIOA0 Pin Setting Register TRDOER1 Bit EA0 CMD1 Setting 0 0 Value Table 7.43 TRDIOB0 Pin Setting Register TRDOER1 TRDFCR Bit EB0 CMD1 CMD0 PWM3 X ...
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R8C/3JC Group Table 7.46 TRDIOA1 Pin Setting Register TRDOER1 TRDFCR Bit EA1 CMD1 CMD0 PWM3 Setting Value Table 7.47 TRDIOB1 Pin Setting Register TRDOER1 TRDFCR Bit EB1 CMD1 ...
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R8C/3JC Group 7.6 Unassigned Pin Handling Table 7.50 lists Unassigned Pin Handling. Table 7.50 Unassigned Pin Handling Pin Name Ports P0_1 to P0_4, P0_6, P0_7, P1, P2_0 to P2_5, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, and P6_6 Port ...
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R8C/3JC Group 8. Bus The bus cycles differ when accessing ROM, RAM, DTC vector area, DTC control data and when accessing SFR. Table 8.1 lists Bus Cycles by Access Area of R8C/3JC Group. ROM, RAM, DTC vector area, DTC control ...
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R8C/3JC Group However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD Timer RD: Registers TRDi ( 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi ...
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R8C/3JC Group 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit: • XIN clock oscillation circuit • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator • Low-speed on-chip oscillator for ...
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R8C/3JC Group CM04 XCIN XCOUT CM04 CM03 S Q CM10 = 1 (stop mode) RESET R Power-on reset Software reset Voltage monitor 0 reset S Q Interrupt request WAIT instruction R CM30 CM13 XIN XOUT CM13 CM05 CM02, CM03, CM04, ...
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R8C/3JC Group fC fC2 fC4 fC32 fOCO40M fOCO128 fOCO fOCO-F fOCO-WDT Timer RA Timer RB INT0 f32 CPU clock Figure 9.2 Peripheral Function Clock REJ09B0602-0100 Rev.1.00 May 12, 2010 Watchdog timer Timer RC Timer RD Timer ...
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R8C/3JC Group 9.2 Registers 9.2.1 System Clock Control Register 0 (CM0) Address 0006h Bit b7 b6 Symbol CM07 CM06 After Reset 0 0 Bit Symbol Bit Name b0 — Reserved bits b1 — b2 CM02 Wait mode peripheral function clock ...
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R8C/3JC Group 9.2.2 System Clock Control Register 1 (CM1) Address 0007h Bit b7 b6 Symbol CM17 CM16 After Reset 0 0 Bit Symbol b0 CM10 All clock stop control bit b1 CM11 XIN-XOUT on-chip feedback resistor select bit b2 CM12 ...
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R8C/3JC Group 9.2.3 System Clock Control Register 3 (CM3) Address 0009h Bit b7 b6 Symbol CM37 CM36 After Reset 0 0 Bit Symbol b0 CM30 Wait control bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...
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R8C/3JC Group CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). Since the XIN clock, XCIN clock, and the on-chip oscillator clock do not stop, the ...
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R8C/3JC Group 9.2.4 Oscillation Stop Detection Register (OCD) Address 000Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 OCD0 Oscillation stop detection enable bit b1 OCD1 Oscillation stop detection interrupt enable bit b2 OCD2 System ...
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R8C/3JC Group 9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) Address 0023h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA00 High-speed on-chip oscillator enable bit b1 FRA01 High-speed on-chip oscillator select bit b2 — ...
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R8C/3JC Group 9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) Address 0025h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA20 High-speed on-chip oscillator frequency switching bit b1 FRA21 b2 FRA22 b3 — Reserved bits ...
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R8C/3JC Group 9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4) Address 0029h Bit b7 b6 Symbol — — After Reset Bit b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the ...
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R8C/3JC Group 9.2.14 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset 0 0 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 0 0 The ...
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R8C/3JC Group 9.2.15 I/O Function Pin Select Register (PINSR) Address 018Fh Bit b7 b6 Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL After Reset 0 0 Bit Symbol b0 XCSEL XCIN/XCOUT pin connect bit b1 — Reserved bit b2 — Nothing is ...
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R8C/3JC Group Procedure for enabling reduced internal power consumption using VCA20 bit Enter low-speed clock mode or Step (1) low-speed on-chip oscillator mode Stop XIN clock and Step (2) high-speed on-chip oscillator clock VCA20 ← 1 Step (3) (internal power ...
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R8C/3JC Group The clocks generated by the clock generation circuits are described below. 9.3 XIN Clock The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral ...
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R8C/3JC Group 9.4 On-Chip Oscillator Clock The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register. 9.4.1 Low-Speed On-Chip Oscillator ...
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R8C/3JC Group 9.5 XCIN Clock The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XCIN clock oscillation circuit is configured by connecting ...
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R8C/3JC Group 9.6 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit. 9.6.1 System Clock The system ...
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R8C/3JC Group 9.6.7 fOCO-S fOCO operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low- speed on-chip oscillator on). In wait mode, ...
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R8C/3JC Group 9.7 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 9.7.1 Standard Operating Mode Standard operating mode is further separated into four modes. ...
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R8C/3JC Group 9.7.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division used as the CPU clock. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 ...
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R8C/3JC Group 9.7.2 Wait Mode Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when count source protection mode is disabled stop. Since the XIN clock, XCIN clock, and on-chip ...
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R8C/3JC Group 9.7.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does ...
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R8C/3JC Group Figure 9.6 shows the Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in CM3 Register is Set to 1 (MCU Enters Wait Mode). To use a peripheral function interrupt to exit wait mode, ...
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R8C/3JC Group Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set ...
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R8C/3JC Group 9.7.3 Stop Mode Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop and the CPU and the peripheral functions operating with these clocks also stop. The least power required to ...
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R8C/3JC Group 9.7.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, ...
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R8C/3JC Group Figure 9.9 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed clock mode CM05 = 0 CM07 = 0 CM13 ...
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R8C/3JC Group 9.8 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table ...
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R8C/3JC Group 9.8.1 How to Use Oscillation Stop Detection Function • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop ...
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R8C/3JC Group Table 9.7 Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Oscillation stop detection ((a) or (b)) Watchdog timer Voltage monitor 1 Voltage monitor 2 NO ...
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R8C/3JC Group Determination of Interrupt sources OCD3 = 1? NO (XIN clock stops) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock)? Set OCD1 bit to 0 (oscillation stop detection (1) interrupt ...
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R8C/3JC Group 9.9 Notes on Clock Generation Circuit 9.9.1 Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 ...
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R8C/3JC Group 9.9.3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b. 9.9.4 Oscillation Circuit Constants Consult the oscillator manufacturer ...
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R8C/3JC Group 10. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows: • Registers protected by PRC0 bit: Registers CM0, CM1, ...
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R8C/3JC Group 11. Interrupts 11.1 Overview 11.1.1 Types of Interrupts Figure 11.1 shows the Types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware Notes: 1. Peripheral function interrupts are generated by the peripheral functions in the MCU not use ...
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R8C/3JC Group 11.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 11.1.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when the UND instruction is executed. 11.1.2.2 Overflow Interrupt An overflow ...
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R8C/3JC Group 11.1.3 Special Interrupts Special interrupts are non-maskable. 11.1.3.1 Watchdog Timer Interrupt A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer. 11.1.3.2 Oscillation Stop Detection Interrupt An oscillation stop detection interrupt ...
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R8C/3JC Group 11.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in ...
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R8C/3JC Group 11.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Table 11.2 Relocatable Vector Tables Interrupt Source ( ...
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R8C/3JC Group 11.2 Registers 11.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0053h (S1TIC), 0054h ...
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R8C/3JC Group 11.2.2 Interrupt Control Register (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC) Address 0041h (FMRDYIC), 0047h (TRCIC), 0048h (TRD0IC), 0049h (TRD1IC), 004Fh (SSUIC/IICIC Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 ILVL0 Interrupt priority level select ...
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R8C/3JC Group 11.2.3 INTi Interrupt Control Register (INTiIC Address 0055h (INT2IC), 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 ILVL0 Interrupt priority level select ...
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R8C/3JC Group 11.3 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 ...
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R8C/3JC Group 11.3.4 Interrupt Sequence The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruction is being executed, the ...
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R8C/3JC Group 11.3.5 Interrupt Response Time Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response ...
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R8C/3JC Group 11.3.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the ...
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R8C/3JC Group The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 11.6 shows the Register Saving Operation. Stack Address [SP] − 5 [SP] − 4 ...
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R8C/3JC Group 11.3.8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved on the stack, are automatically restored. The program, that was running ...
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R8C/3JC Group 11.3.10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 11.8 shows the Interrupt Priority Level Selection Circuit. Priority level of interrupts Voltage monitor 1 UART2 bus ...
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R8C/3JC Group 11.4 INT Interrupt 11.4.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register (enabled). The ...
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R8C/3JC Group 11.4.3 External Input Enable Register 0 (INTEN) Address 01FAh Bit b7 b6 Symbol INT3PL INT3EN After Reset 0 0 Bit Symbol b0 INT0EN INT0 input enable bit b1 INT0PL INT0 input polarity select bit b2 INT1EN INT1 input ...
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R8C/3JC Group 11.4.4 INT Input Filter Select Register 0 (INTF) Address 01FCh Bit b7 b6 Symbol INT3F1 INT3F0 After Reset 0 0 Bit Symbol b0 INT0F0 INT0 input filter select bit b1 INT0F1 b2 INT1F0 INT1 input filter select bit ...
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R8C/3JC Group 11.4.5 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in register INTF. The INTi level is sampled every sampling clock cycle ...
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R8C/3JC Group 11.5 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit wait or ...
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R8C/3JC Group 11.5.1 Key Input Enable Register 0 (KIEN) Address 01FEh Bit b7 b6 Symbol KI3PL KI3EN After Reset 0 0 Bit Symbol b0 KI0EN KI0 input enable bit b1 KI0PL KI0 input polarity select bit b2 KI1EN KI1 input ...
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R8C/3JC Group 11.6 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register ( 1). This interrupt is used as a break function ...
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R8C/3JC Group 11.6.1 Address Match Interrupt Enable Register i (AIERi Address 01C3h (AIER0), 01C7h (AIER1) Bit b7 b6 Symbol — — After Reset 0 0 Symbol — — After Reset 0 0 Bit Symbol b0 ...
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R8C/3JC Group 11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication Unit Interrupt, I (Interrupts with Multiple Interrupt Request Sources) The timer RC interrupt, timer RD (timer RD0) interrupt, timer RD (timer RD1) interrupt, synchronous serial communication unit interrupt, ...
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R8C/3JC Group As with other maskable interrupts, the timer RC interrupt, timer RD (timer RD0) interrupt, timer RD (timer RD1) interrupt, synchronous serial communication unit interrupt, I are controlled by the combination of the I flag, IR bit, bits ILVL0 ...
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R8C/3JC Group 11.8 Notes on Interrupts 11.8.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the ...
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R8C/3JC Group 11.8.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after ...
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R8C/3JC Group 11.8.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that register are generated interrupt request may be generated, disable the interrupt before ...
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R8C/3JC Group 12. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode. This function prevents the flash memory from being read, rewritten, or ...
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R8C/3JC Group 12.2 Functions The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and ...