R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 584

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
26.6
Figure 26.16
Figures 26.16 to 26.19 show Examples of Register Setting When Using I
Examples of Register Setting
Register Setting Example in Master Transmit Mode (I
ICCR1 register
ICCR2 register
ICSR register
ICSR register
ICCR2 register
ICCR1 register
ICSR register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Read ACKBR bit in ICIER register
Read BBSY bit in ICCR2 register
Read TEND bit in ICSR register
Read TDRE bit in ICSR register
Read TEND bit in ICSR register
Read STOP bit in ICSR register
No
No
No
No
No
No
ACKBR = 0?
Initial setting
Yes
BBSY = 0?
TEND = 1?
TDRE = 1?
TEND = 1?
Last byte?
STOP = 1?
TDRE bit ← 0
Transmit
mode?
MST bit ← 1
BBSY bit ← 1
TEND bit ← 0
BBSY bit ← 0
MST bit ← 0
TRS bit ← 1
SCP bit ← 0
SCP bit ← 0
TRS bit ← 0
STOP bit ← 0
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Master receive mode
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the SSUIICSR register to 1.
• Set the MSTIIC bit in the MSTCR register to 0.
(1) Determine the state of the SCL and SDA lines.
(2) Set to master transmit mode.
(3) Generate a start condition.
(4) Set the transmit data of the 1st byte
(5) Wait until 1 byte of data is transmitted.
(6) Determine the ACKBR bit from the specified
(7) Set the transmit data after 2nd byte
(8) Wait until the ICRDT register is empty.
(9) Set the transmit data of the last byte.
(10) Wait for end of transmission of the last byte.
(11) Set the TEND bit to 0.
(12) Set the STOP bit to 0.
(13) Generate a stop condition.
(14) Wait until a stop condition is generated.
(15) Set to slave receive mode.
(slave address + R/W).
slave device.
(except the last byte).
Set the TDRE bit to 0.
2
C bus interface.
2
C bus Interface Mode)
26. I
Page 553 of 715
2
C bus Interface