R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 425

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
20.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode
20.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode
b15 to b0 Count a count source. Count operation is incremented.
After Reset
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 0144h (TRDIER0), 0154h (TRDIER1)
Address 0147h to 0146h
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
The TRD1 register is not used in PWM3 mode.
Symbol
Symbol
Symbol
Symbol
Bit
IMIEA
IMIEB
IMIEC
IMIED
Bit
Bit
OVIE
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
—
—
—
b15
b7
b7
—
—
—
1
0
0
Input capture/compare match interrupt
enable bit A
Input capture/compare match interrupt
enable bit B
Input capture/compare match interrupt
enable bit C
Input capture/compare match interrupt
enable bit D
Overflow/underflow interrupt enable
bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
b14
b6
b6
—
—
—
1
0
0
Bit Name
b13
b5
—
b5
—
—
1
0
0
Function
OVIE
b12
b4
b4
—
—
0
0
0
0: Disable interrupt (IMIA) by the IMFA bit
1: Enable interrupt (IMIA) by the IMFA bit
0: Disable interrupt (IMIB) by the IMFB bit
1: Enable interrupt (IMIB) by the IMFB bit
0: Disable interrupt (IMIC) by the IMFC bit
1: Enable interrupt (IMIC) by the IMFC bit
0: Disable interrupt (IMID) by the IMFD bit
1: Enable interrupt (IMID) by the IMFD bit
0: Disable interrupt (OVI) by the OVF bit
1: Enable interrupt (OVI) by the OVF bit
IMIED
b11
b3
b3
—
—
0
0
0
IMIEC
b10
b2
b2
—
—
0
0
0
Function
IMIEB
b1
b1
b9
—
—
0
0
0
0000h to FFFFh
IMIEA
Setting Range
b0
b0
b8
—
—
0
0
0
Page 394 of 715
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—