R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 474

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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RENESAS/瑞萨
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Part Number:
R5F213J6CNNP#U0
Manufacturer:
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Quantity:
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 22.7
• Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit)
UiBRG output
Transfer clock
SiRIC register
UiC1 register
UiC1 register
RE bit in
RI bit in
IR bit in
RXDi
The above applies when :
Receive Timing in UART Mode
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (one stop bit)
i = 0 or 1
Reception starts when a transfer clock is
generated at the falling edge of the start bit.
Start bit
“L” is determined.
D0
Set to 0 when an interrupt request is acknowledged or by a program.
Receive data taken in
D1
Data transfer from UARTi receive register to UiRB register
22. Serial Interface (UARTi (i = 0 or 1))
D7
Stop bit
Page 443 of 715

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