R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 229

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 15.8
15.3.4
Table 15.6
j =0 to 23
DTC block size register j
DTC transfer count register j
DTC transfer count reload
register j
DTC source address register j
DTC destination address
register j
One to 256 bytes of data are transferred by one activation. The number of transfer times can be 1 to 256. When
the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed, an interrupt
request for the CPU is generated during DTC operation.
Table 15.6 lists Register Functions in Normal Mode.
Figure 15.8 shows Data Transfers in Normal Mode.
X: 0 or 1
DTCCR register
Bits b3 to b0 in
Normal Mode
Register
00X0b
01X0b
10X0b
11X0b
Data Transfers in Normal Mode
Register Functions in Normal Mode
Transfer source
SRC
Source address
Incremented
Incremented
control
Fixed
Fixed
DTBLSj
DTCCTj
DTRLDj
DTSARj
DTDARj
Symbol
Destination address
Transfer
Incremented
Incremented
control
Fixed
Fixed
Transfer destination
Size of the data block to be transferred by one activation
Number of times of data transfers
Not used
Data transfer source address
Data transfer destination address
DST
Source address
after transfer
SRC+N
SRC+N
SRC
SRC
Size of the data block to be transferred
by one activation (N bytes)
DTBLSj = N
DTSARj = SRC
DTDARj = DST
j = 0 to 23
Function
Destination address
after transfer
DST+N
DST+N
DST
DST
Page 198 of 715
15. DTC

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