R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 322

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 19.19
• TRCGRB register setting value greater than TRCGRA
register setting value
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TSTART bit in
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output by compare match with the TRCGRC register, “L” output by compare
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
IMFA bit in
IMFB bit in
IMFC bit in
match with the TRCGRB register).
TRC register value
0000h
Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
0
n
m
p
“L” initial
output
m+1
p+1
“H” output at TRCGRC register
compare match
Set to 0 by a
program
No compare match with
TRCGRB register, so
“H” output continues
• TRCGRC register setting value greater than TRCGRA
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
register setting value
TSTART bit in
IMFA bit in
IMFB bit in
IMFC bit in
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRC register value
0000h
0
No compare match
with TRCGRC register,
so “L” output continues
p
m
n
“L” initial
output
m+1
n+1
“L” output at
TRCGRB register
compare match
with no change.
Page 291 of 715
19. Timer RC

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