R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 547
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 25.10
25.5.1
Figure 25.10 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive
operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0
(receive disabled), and initialize the synchronous serial communication unit.
To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.
Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR
register.
(1)
(2)
Initialization in 4-Wire Bus Communication Mode
Note:
Initialization in 4-Wire Bus Communication Mode
SSER register
1. Write 0 after reading 1 to set the ORER bit to 0.
SSMR register
SSCRH register
SSMR2 register
SSSR register
SSMR2 register
SSCRH register
SSER register
Set bits CPHS and CPOS
MLS bits ← 0
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
Start
Set bits CKS0 to CKS2
Set RSSTP bit
End
SCKS bit ← 1
Set bits SOOS, CSS0 to
CSS1, and BIDE
ORER bit ← 0
SSUMS bit ← 1
RE bit ← 0
TE bit ← 0
Set MSS bit
(1)
25. Synchronous Serial Communication Unit (SSU)
(2) Set the BIDE bit to 1 in bidirectional mode and
(1) The MLS bit is set to 0 for MSB-first transfer.
set the I/O of the SCS pin by bits CSS0 and
CSS1.
The clock polarity and phase are set by bits
CPHS and CPOS.
Page 516 of 715
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