R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 422
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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- Download datasheet (8Mb)
R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
20.8.9
Note:
1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 013Dh
TRDOCR register is set.
Write to the TRDOCR register when both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0
(count stops).
Symbol
Symbol
Bit
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
Timer RD Output Control Register (TRDOCR) in PWM3 Mode
TOD1
b7
0
TRDIOA0 output level select bit
TRDIOB0 output level select bit
TRDIOC0 initial output level select bit These bits are disabled in PWM3 mode.
TRDIOD0 initial output level select bit
TRDIOA1 initial output level select bit
TRDIOB1 initial output level select bit
TRDIOC1 initial output level select bit
TRDIOD1 initial output level select bit
TOC1
b6
0
Bit Name
TOB1
b5
0
TOA1
b4
0
(1)
(1)
0: Active level “H”,
1: Active level “L”,
0: Active level “H”,
1: Active level “L”,
TOD0
b3
0
initial output “L”,
output “H” at compare match with the TRDGRA1
register,
output “L” at compare match with the TRDGRA0
register
initial output “H”,
output “L” at compare match with the TRDGRA1
register,
output “H” at compare match with the TRDGRA0
register
initial output “L”,
output “H” at compare match with the
TRDGRB1register,
output “L” at compare match with the TRDGRB0
register
initial output “H”,
output “L” at compare match with the TRDGRB1
register,
output “H” at compare match with the TRDGRB0
register
TOC0
b2
0
Function
TOB0
b1
0
TOA0
b0
0
Page 391 of 715
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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