R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 417

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
20.8.1
Notes:
20.8.2
Note:
1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I
2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h
3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).
4. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h
1. Enabled when in timer mode.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0008h
Address 0135h
0193h to 019Dh) is disabled.
to 015Fh) is disabled.
to 0133h) is disabled.
Symbol
Symbol ITCLK1
MSTTRD Timer RD standby bit
MSTTRC Timer RC standby bit
Symbol
MSTIIC SSU, I
Symbol
ITCLK0 Timer RD0 fC2 select bit
ITCLK1 Timer RD1 fC2 select bit
Bit
Bit
Module Standby Control Register (MSTCR)
Timer RD Control Expansion Register (TRDECR)
—
—
—
—
—
—
—
—
—
—
—
b7
b7
—
0
0
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
2
C bus standby bit
b6
b6
—
—
0
0
Bit Name
Bit Name
MSTTRC MSTTRD MSTIIC
b5
b5
—
0
0
b4
b4
—
0
0
0: TRDCLK input selected
1: fC2 selected
0: TRDCLK input selected
1: fC2 selected
ITCLK0
0: Active
1: Standby
0: Active
1: Standby
0: Active
1: Standby
b3
b3
0
0
(1)
(2, 3)
(4)
(1)
(1)
b2
b2
—
—
0
0
2
Function
C bus associated registers (addresses
Function
b1
—
b1
—
0
0
b0
b0
—
—
0
0
Page 386 of 715
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—