R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 602

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 27.9
27.4.3
LINCR register
TRAIC register
LINST register
BCDCT flag in
Transfer clock
U0C1 register
LINE bit in
RXD0 pin
TXD0 pin
The bus collision detection function can be used if UART0 is enabled for transmission (TE bit in U0C1 register
= 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register to 1
(bus collision detection enabled).
Figure 27.9 shows an Operating Example When Bus Collision is Detected.
TE bit in
IR bit in
Bus Collision Detection Function
Operating Example When Bus Collision is Detected
Set to 1 by a program.
Set to 1 by a program.
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B2CLR bit in LINST register.
27. Hardware LIN
Page 571 of 715

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