R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 559

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
26.2.4
26.2.5
b7 to b0
b7 to b0
After Reset
After Reset
Bit
Bit
Address 0194h
Address 0196h
Symbol
Symbol
Bit
Bit
This register stores transmit data.
When the ICDRS register is detected as empty, the stored transmit data item is transferred to the
ICDRS register and data transmission starts.
When the next unit of transmit data is written to the ICDRT register while data is transmitted to the
ICDRS register, continuous transmission is enabled.
When the MLS bit in the ICMR register is set to 1 (data transfer with LSB-first), the MSB-LSB
inverted data is read after the data is written to the ICDRT register.
This register stores receive data.
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
IIC bus Transmit Data Register (ICDRT)
IIC bus Receive Data Register (ICDRR)
b7
b7
—
—
1
1
b6
b6
—
—
1
1
b5
—
b5
—
1
1
b4
b4
—
—
1
1
Function
Function
b3
b3
—
—
1
1
b2
b2
—
—
1
1
b1
b1
—
—
1
1
b0
b0
—
—
1
1
26. I
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2
C bus Interface
R/W
R/W
R/W
R