R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 385

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Table 20.11
j = A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Selectable functions
Reset Synchronous PWM Mode Specifications
Item
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
External signal input to the TRDCLK pin (valid edge selected by a
program)
The TRD0 register is incremented (the TRD1 register is not used).
PWM period
Active level width of normal-phase : 1/fk × (m-n)
Active level width of counter-phase: 1/fk × (n+1)
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit when the CSEL0 bit in
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (The content of the TRD0 register matches content
• The TRD0 register overflows
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every PWM period
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• The normal-phase and counter-phase active level and initial output
• Buffer operation (Refer to 20.2.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse
• A/D trigger generation
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output),
the TRDSTR register is set to 1. (The PWM output pin outputs the
initial output level selected by bits OLS0 and OLS1 in the TRDFCR
register.)
stops at the compare match in the TRDGRA0 register. (The PWM
output pin outputs the initial output level selected by bits OLS0 and
OLS1 in the TRDFCR register.)
of registers TRDGRj0, TRDGRA1, and TRDGRB1)
level are selected individually.
Output Forced Cutoff .)
Counter-phase
Normal-phase
Value set in the TRDGRA1 register (PWM2 output),
Value set in the TRDGRB1 register (PWM3 output)
n+1
m+1
Specification
m-n
: 1/fk × (m+1)
(When “L” is selected as the active level)
Page 354 of 715
20. Timer RD