R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 470

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
22.4
Table 22.5
i = 0 or 1
Note:
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 22.5 lists the UART Mode Specifications. Table 22.6 lists the Registers Used and Settings in UART Mode.
1. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined.
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
• Character bits (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bits: Selectable among 1 or 2 bits
• The CKDIR bit in the UiMR register is set to 0 (internal clock): fj/(16(n+1))
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
• To start transmission, the following requirements must be met:
• To start reception, the following requirements must be met:
• For transmission: One of the following can be selected.
• For reception:
• Overrun error
• Parity error
fj = f1, f8, f32, fC n = setting value in the UiBRG register: 00h to FFh
fEXT: Input from the CLKi pin,
n = setting value in the UiBRG register: 00h to FFh
- The TE bit in the UiC1 register is set to 1 (transmission enabled).
- The TI bit in the UiC1 register is set to 0 (data present in the UiTB
- The RE bit in the UiC1 register is set to 1 (reception enabled).
- Start bit detection
- The UiIRS bit is set to 0 (transmit buffer empty):
- The UiIRS bit is set to 1 (transfer completed):
When data is transferred from the UARTi receive register to the UiRB
register (at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data
before reading the UiRB register and receive the bit one before the last
stop bit of the next unit of data.
This error occurs when parity is enabled, and the number of 1’s in the
parity and character bits do not match the set number of 1’s.
register).
When data is transferred from the UiTB register to the UARTi transmit
register (at start of transmission).
When data transmission from the UARTi transmit register is completed.
(1)
Specification
22. Serial Interface (UARTi (i = 0 or 1))
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