R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 594
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
27.3.2
Notes:
27.3.3
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once.
3. Inputs to timer RA and UART0 are disabled immediately after the LINE bit is set to 1 (LIN operation starts).
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0106h
Address 0107h
(Refer to Figure 27.3 Header Field Transmission Flowchart Example (1) and Figure 27.7 Header Field
Reception Flowchart Example (2) .)
Symbol
Symbol
LSTART Synch Break detection start bit
BCDCT Bus collision detection flag
Symbol
RXDSF RXD0 input status flag
Symbol
SFDCT Synch Field measurement-completed
SBDCT Synch Break detection flag
B0CLR SFDCT bit clear bit
B1CLR SBDCT bit clear bit
B2CLR BCDCT bit clear bit
Bit
Bit
SBIE
BCIE
SFIE
LINE
MST
SBE
LIN Control Register (LINCR)
LIN Status Register (LINST)
—
—
LINE
b7
b7
—
0
0
Synch Field measurement-completed
interrupt enable bit
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
RXD0 input unmasking timing
select bit
(effective only in slave mode)
LIN operation mode setting bit
LIN operation start bit
flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
MST
b6
b6
—
0
0
Bit Name
Bit Name
B2CLR
SBE
b5
b5
0
0
LSTART
B1CLR
b4
b4
(2)
(1)
0
0
0: Synch Field measurement-completed interrupt
1: Synch Field measurement-completed interrupt
0: Synch Break detection interrupt disabled
1: Synch Break detection interrupt enabled
0: Bus collision detection interrupt disabled
1: Bus collision detection interrupt enabled
0: RXD0 input enabled
1: RXD0 input disabled
When this bit is set to 1, timer RA input is enabled
and RXD0 input is disabled.
When read, the content is 0.
0: Unmasked after Synch Break detected
1: Unmasked after Synch Field measurement
0: Slave mode
1: Master mode
0: LIN operation stops
1: LIN operation starts
When this bit is set to 1, Synch Field measurement
is completed.
when this bit is set to 1, Synch Break is detected or
Synch Break generation is completed.
When this bit is set to 1, bus collision is detected.
When this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
RXDSF
B0CLR
b3
disabled
enabled
completed
(Synch Break detection circuit operation)
(timer RA output OR’ed with TXD0)
b3
0
0
BCDCT
BCIE
b2
b2
0
0
Function
SBDCT
Function
SBIE
(3)
b1
b1
0
0
SFDCT
SFIE
b0
b0
0
0
27. Hardware LIN
Page 563 of 715
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R
R
R
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