R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 448

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Table 21.4
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TREO pin function
Read from timer
Write to timer
Selectable functions
Item
Output Compare Mode Specifications
f4, f8, f32, fC4
• Increment
• When the 8-bit counter content matches with the TREMIN register
• When RCS2 = 0 (4-bit counter is not used)
• When RCS2 = 1 (4-bit counter is used)
fi: Frequency of count source
n: Setting value of TREMIN register
1 (count starts) is written to the TSTART bit in the TRECR1 register
0 (count stops) is written to the TSTART bit in the TRECR1 register
When the 8-bit counter content matches with the TREMIN register content
Select any one of the following:
• Programmable I/O ports
• Output f2, fC, f4, or f8
• Compare output
When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
• Select use of 4-bit counter
• Compare output function
content, the value returns to 00h and count continues.
The count value is held while count stops.
1/fi x 2 x (n+1)
1/fi x 32 x (n+1)
Every time the 8-bit counter value matches the TREMIN register value,
TREO output polarity is reversed. The TREO pin outputs “L” after reset
is deasserted and the timer RE is reset by the TRERST bit in the
TRECR1 register. Output level is held by setting the TSTART bit to 0
(count stops).
Specification
Page 417 of 715
21. Timer RE

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