R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 195

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
As with other maskable interrupts, the timer RC interrupt, timer RD (timer RD0) interrupt, timer RD (timer RD1)
interrupt, synchronous serial communication unit interrupt, I
are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each
interrupt source is generated by a combination of multiple interrupt request sources, the following differences from
other maskable interrupts apply:
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•
•
•
•
Refer to chapters of the individual peripheral functions (19. Timer RC, 20. Timer RD, 25. Synchronous Serial
Communication Unit (SSU), 26. I
register.
For the interrupt control register, refer to 11.3 Interrupt Control.
When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt
enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR
bit is set to 0 (no interrupt requested).
That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
retained.
Also, the IR bit is not set to 0 even if 0 is written to this bit.
Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
The IR bit is also not automatically set to 0 when the interrupt is acknowledged.
Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to
set individual bits in the status register to 0.
When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set
to 1, the IR bit remains 1.
When multiple bits in the enable register are set to 1, use the status register to determine which request source
causes an interrupt.
2
C bus Interface, and 31. Flash Memory) for the status register and enable
2
C bus interface interrupt, and flash memory interrupt
Page 164 of 715
11. Interrupts