R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 667
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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- Download datasheet (8Mb)
R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 31.14
31.4.11.6 Read Lock Bit Status Command
This command is used to read the lock bit status of any address in the program ROM area.
When 71h written in the first bus cycle and D0h is written in the second cycle to the starting block address, the
lock bit status of the specified block is stored in the LBDATA bit in the FST register. After the FST7 bit in the
FST register has been set to 1 (ready), read the LBDATA bit.
Figure 31.14 shows a Read Lock Bit Status Flowchart.
Read Lock Bit Status Flowchart
Write the command code 71h
Write D0h to the starting
block address
Full status check
Completed
FST7 = 1?
Start
Yes
No
FST7: Bit in FST register
31. Flash Memory
Page 636 of 715
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