R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 173
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
11.1.3
11.1.4
11.1.3.1
11.1.3.2
11.1.3.3
11.1.3.4
11.1.3.5
11.1.3.6
Special interrupts are non-maskable.
A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer.
An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the
oscillation stop detection function, refer to 9. Clock Generation Circuit.
A voltage monitor 1 interrupt is generated by the voltage detection circuit. A non-maskable or maskable
interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the voltage detection circuit,
refer to 6. Voltage Detection Circuit.
A voltage monitor 2 interrupt is generated by the voltage detection circuit. A non-maskable or maskable
interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the voltage detection circuit,
refer to 6. Voltage Detection Circuit.
Do not use these interrupts. They are provided exclusively for use by development tools.
An address match interrupt is generated immediately before executing an instruction that is stored at an address
indicated by registers RMAD0 to RMAD1 if the AIER00 bit in the AIER0 register or the AIER10 bit in the
AIER1 register is set to 1 (address match interrupt enabled).
For details of the address match interrupt, refer to 11.6 Address Match Interrupt.
A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts
are maskable. Refer to Table 11.2 Relocatable Vector Tables for sources of the corresponding peripheral
function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral
functions.
Special Interrupts
Peripheral Function Interrupts
Watchdog Timer Interrupt
Oscillation Stop Detection Interrupt
Voltage Monitor 1 Interrupt
Voltage Monitor 2 Interrupt
Single-Step Interrupt, and Address Break Interrupt
Address Match Interrupt
Page 142 of 715
11. Interrupts
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