R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 589

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
26.8
Figure 26.21
Table 26.7
1Tcyc = 1/f1(s)
When the I
•
•
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 26.21 shows the Bit Synchronization Circuit Timing and Table 26.7 lists the Time between Changing SCL
Signal from “L” Output to High-Impedance and Monitoring SCL Signal.
The SCL signal is driven L level by a slave device
The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Bit Synchronization Circuit
CKS3
2
C bus interface is set to master mode, the high-level period may become shorter if:
0
1
Bit Synchronization Circuit Timing
Monitoring SCL Signal
Time between Changing SCL Signal from “L” Output to High-Impedance and
ICCR1 Register
SCL monitor timing
Reference clock of
Internal SCL
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
SCL Monitoring Time
26. I
Page 558 of 715
2
C bus Interface