R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 220

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
15.2.7
i = 0 to 6
Note:
Table 15.2
1. For the operation of this bit, refer to 15.3.7 Interrupt Sources.
After Reset
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
Register
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Ch (DTCEN4),
The DTCENi registers enable/disable DTC activation by interrupt sources. Table 15.2 shows Correspondences
between Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt Sources.
Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 DTCENi2 DTCENi1 DTCENi0
DTCENi0 DTC activation enable bit
DTCENi1
DTCENi2
DTCENi3
DTCENi4
DTCENi5
DTCENi6
DTCENi7
Symbol
Bit
DTC Activation Enable Register i (DTCENi) (i = 0 to 6)
SSU/I
receive data
008Dh (DTCEN5), 008Eh (DTCEN6)
Timer RD1
DTCENi7
Timer RC
compare-
compare-
Key input
match C
match C
capture/
capture/
Sources
Correspondences between Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt
input-
input-
INT0
b7
full
Bit
0
2
C bus
SSU/I
conversion
data empty
Timer RD1
Timer RC
DTCENi6
compare-
compare-
Timer RA
match D
match D
b6
transmit
capture/
capture/
0
input-
input-
INT1
A/D
Bit
2
C bus
Bit Name
b5
0
Timer RD0
DTCENi5
reception
Monitor 2
compare-
Timer RE
capture/
match A
UART0
Voltage
input-
INT2
Bit
(1)
b4
0
transmission
Timer RD0
DTCENi4
Monitor 1
compare-
Timer RB
capture/
match B
Voltage
UART0
input-
INT3
0: Activation disabled
1: Activation enabled
Bit
b3
0
Flash ready
Timer RD0
DTCENi3
compare-
reception
capture/
match C
UART1
status
input-
Bit
b2
0
Function
transmission
Timer RD0
DTCENi2
compare-
match D
capture/
UART1
input-
b1
0
Bit
b0
Timer RD1
Timer RC
0
DTCENi1
reception
compare-
compare-
match A
match A
capture/
capture/
UART2
input-
input-
Bit
Page 189 of 715
transmission
Timer RD1
DTCENi0
Timer RC
compare-
compare-
capture/
match B
capture/
match B
UART2
input-
input-
Bit
15. DTC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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