R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 168

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
9.9
9.9.1
9.9.2
To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least four NOP instructions following the JMP.B instruction after the instruction which sets the CM10
bit to 1.
• Program example to enter stop mode
To enter wait mode by setting the CM30 bit to 1, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite
mode disabled) before setting the CM30 bit to 1.
To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode
disabled) and then execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the instruction to
set the CM30 bit to 1 (MCU enters wait mode) or the WAIT instruction, and then the program stops. Insert at
least four NOP instructions after the instruction to set the CM30 bit to 1 (MCU enters wait mode) or the WAIT
instruction.
• Program example to execute the WAIT instruction
• Program example to execute the instruction to set the CM30 bit to 1
Notes on Clock Generation Circuit
Stop Mode
Wait Mode
LABEL_001:
BCLR
BCLR
BSET
FSET
BSET
JMP.B
NOP
NOP
NOP
NOP
BCLR
BCLR
FSET
WAIT
NOP
NOP
NOP
NOP
BCLR
BCLR
BSET
FCLR
BSET
NOP
NOP
NOP
NOP
BCLR
FSET
1,FMR0
7,FMR2
0,PRCR
I
0,CM1
LABEL_001
1,FMR0
7,FMR2
I
1, FMR0
7, FMR2
0, PRCR
I
0, CM3
0, PRCR
I
; CPU rewrite mode disabled
; Low-current-consumption read mode disabled
; Writing to CM1 register enabled
; Interrupt enabled
; Stop mode
; CPU rewrite mode disabled
; Low-current-consumption read mode disabled
; Interrupt enabled
; Wait mode
; CPU rewrite mode disabled
; Low-current-consumption read mode disabled
; Writing to CM3 register enabled
; Interrupt disabled
; Wait mode
; Writing to CM3 register disabled
; Interrupt enabled
9. Clock Generation Circuit
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