R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 601

MCU 1KB FLASH 32K ROM 36-QFN

R5F213J6CNNP#U0

Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet

Specifications of R5F213J6CNNP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 27.8
Hardware LIN
UART0
Timer RA Set the Synch Break width again
UART0
(UART) mode ID field reception
Communication via UART0
Clock asynchronous serial interface
Set the UART0 communication rate
U0BRG register
TRAPRE register
TRA register
Header Field Reception Flowchart Example (3)
Read the Synch Field measurement-
completed flag
SFDCT flag in LINST register
SFDCT = 1?
YES
B
NO
A Synch Field for the hardware LIN
is measured.
A timer RA interrupt can be used.
(The SBDCT flag is set when
the timer RA counter underflows.)
If the SBE bit in the LINCR register
is set to 1 (unmasked after Synch
Field measurement completed),
timer RA can be used in timer mode
after the SFDCT flag in the LINST
register is set to 1 and the RXDSF
flag is set to 0.
Set a communication rate based on
the Synch Field measurement
result.
Communication is performed via
UART0.
(The SBDCT flag is set when
the timer RA counter underflows.)
27. Hardware LIN
Page 570 of 715

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