R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 248

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
17.5.1
Notes:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
2. Make the following settings to use event input enabled at INT2 level:
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0101h
• Set the INT2EN bit in the INTEN register to 1 (INT2 input enabled) and the INT2PL bit to 0 (one edge).
• Set the INT2 polarity by the POL bit in the INT2IC register.
• Set the PDi_j (j = 2 or 6) bit in the PDi (i = 3 or 6) register for the port assigned as the INT2 pin to 0 (input
• Select the INT2 digital filter by bits INT2F1 to INT2F0 in the INTF register.
The IR bit in the INT2IC register is set to 1 (interrupt requested) in accordance with the setting of the POL bit in
the INT2IC register and the INT2PL bit in the INTEN register and a change in the INT2 pin input (refer to 11.8
Notes on Interrupts).
For details on interrupts, refer to 11. Interrupts.
Symbol TIOGT1
When the POL bit is set 0 (falling edge selected), the event input for the INT2 high-level period is enabled.
When the POL bit is set 1 (rising edge selected), the event input for the INT2 low-level period is enabled.
mode).
TEDGSEL TRAIO polarity switch bit
TOPCR
TOENA
TIOGT0
TIOGT1
Bit
Symbol
TIPF0
TIPF1
Timer RA I/O Control Register (TRAIOC) in Event Counter Mode
—
b7
0
TRAIO output control bit
TRAO output enable bit
Reserved bit
TRAIO input filter select bit
TRAIO event input control bit
TIOGT0
b6
0
Bit Name
TIPF1
b5
0
TIPF0
(1)
b4
0
1: Starts counting at falling edge of the TRAIO input
Set to 0 in event counter mode.
0: TRAO output disabled
1: TRAO output
Set to 0.
b5 b4
b7 b6
0: Starts counting at rising edge of the TRAIO input
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
0 0: Event input always enabled
0 1: Event input enabled at INT2 level
1 0: Event input enabled for “L” period of TRCIOD
1 1: Do not set.
and TRAO starts output at “L”
and TRAO starts output at “H”
(timer RC output)
b3
—
0
TOENA
b2
0
Function
TOPCR TEDGSEL
b1
0
b0
0
(2)
Page 217 of 715
17. Timer RA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W