R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 334

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
20.3
Figure 20.7
The input capture function measures the external signal width and period. The content of the TRDi register
(counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = A, B, C, or D) pin
external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji
register, the input capture function, or any other mode or function, can be selected for each individual pin.
The TRDGRA0 register can also select fOCO128 signal as input-capture trigger input.
Figure 20.7 shows a Block Diagram of Input Capture Function, Table 20.5 lists the Input Capture Function
Specifications. Figure 20.8 shows an Operating Example of Input Capture Function.
i = 0 or 1
Notes 1: When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
TRDIOAi
Input Capture Function
TRDIOCi
TRDIODi
TRDIOBi
fOCO-S
fOCO-F
2: When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of
3: The trigger input of the TRDGRA0 register can select the TRDIOA0 pin input or fOCO128 signal.
or
the TRDGRAi register).
the TRDGRBi register).
(3)
Block Diagram of Input Capture Function
Only TRDGRA0 available
Divided
by 128
selection
selection
selection
selection
Edge
Edge
Edge
Edge
fOCO128
IOA3 = 0
IOA3 = 1
(Note 1)
(Note 2)
Input capture signal
Input capture signal
Input capture signal
Input capture signal
TRDGRAi
TRDGRCi
TRDGRBi
TRDGRDi
register
register
register
register
TRDi register
Page 303 of 715
20. Timer RD