R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 233
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
15.3.9
Table 15.9
Notes:
Table 15.10
Operation
Data read
Data write
Vector Read
1. For the number of clock cycles required for data read/write, refer to Table 15.10 Number of Clock
2. For the number of clock cycles required for control data write-back, refer to Table 15.8
Table 15.9 lists the Operations Following DTC Activation and Required Number of Cycles for each operation.
Table 15.10 lists the Number of Clock Cycles Required for Data Transfers.
Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N,
(1) When N = 2n (even), two-byte transfers are performed n times.
(2) When N = 2n + 1 (odd), two-byte transfers are performed n times followed by one time of one-byte
From Tables 15.9 and 15.10, the total number of required execution cycles can be obtained by the following
formula:
Number of required execution cycles = 1 + Σ[formula A] + 2
Σ: Sum of the cycles for the number of transfer times performed by one activation source ([the number of
transfer times for which CHNE is set to 1] + 1)
(1) For N = 2n (even)
(2) For N = 2n+1 (odd)
To read data from or write data to the register that to be accessed in 16-bit units, set an even value of 2 or greater
to the DTBLSj (j = 0 to 23) register.
The DTC performs accesses in 16-bit units.
Cycles Required for Data Transfers .
Specifications of Control Data Write-Back Operation .
1
transfer.
Formula A = J + n • SK2 + n • SL2
Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1
J: Number of cycles required to read control data (5 cycles) + number of cycles required to write back control data
Number of DTC Execution Cycles
1-byte SK1
2-byte SK2
1-byte SL1
2-byte SL2
Transfers
Unit of
Operations Following DTC Activation and Required Number of Cycles
Number of Clock Cycles Required for Data Transfers
(During DTC Transfers) Internal ROM
Address
Read
Even
Internal RAM
1
1
5
Control Data
1
1
Address
Odd
2
2
Write-back
(Note 2)
(Program ROM)
—
—
1
2
(Data flash)
Data Read
(Note 1)
Internal
ROM
—
—
2
4
SFR (Word Access)
Address
Even
2
2
Data Write
2
2
(Note 1)
Address
Odd
4
4
Access)
(Byte
SFR
2
4
2
4
Internal Operation
(DTC control data area)
Address
Even
Page 202 of 715
1
1
1
SFR
1
1
Address
Odd
15. DTC
2
2
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