R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 499

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 23.7
(1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
(2) Transmit Timing Example When Transfer Data 9 Bits is Long (Parity Disabled, Two Stop Bits)
The above applies when:
The above applies when:
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 1 (two stop bits)
• CRD bit in U2C0 register = 1 (CTS/RTS function disabled)
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the transmit buffer is empty)
• PRYE bit in U2MR register = 1 (parity enabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• U2IRS bit in U2C1 register = 1 (interrupt request generation when transmission is completed)
Transfer clock
S2TIC register
U2C1 register
U2C1 register
U2C0 register
TXEPT bit in
Transfer clock
S2TIC register
U2C1 register
U2C1 register
U2C0 register
TXEPT bit in
TE bit in
IR bit in
TI bit in
TXD2
TE bit in
IR bit in
TI bit in
CTS2
TXD2
Transmit Timing in UART Mode
Start bit
Data is set in U2TB register.
ST
Start bit
D0 D1
ST
Set to 0 when an interrupt request is acknowledged or by a program.
D0
Data is set in U2TB register.
D2 D3
D1
TC
D2 D3
TC
D4 D5
D4 D5
The transfer clock stops once because “H” is applied to CTS pin when the stop bit is verified.
The transfer clock resumes running immediately after “L” is applied to CTS pin.
D6
D7
D6
D8
D7
Stop
Parity
bit
SP
P
bit
SP
SP
Set to 0 when an interrupt request is acknowledged or by a program.
Stop
Stop
bit
bit
Data transfer from U2TB register
to UART2 transmit register
ST
ST
Data transfer from U2TB register
to UART2 transmit register
D0 D1
D0 D1
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
fj: Frequency of U2BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U2BRG count source (external clock)
n: Setting value in U2BRG
D2 D3
D2 D3
fj: Frequency of U2BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U2BRG count source (external clock)
n: Setting value in U2BRG
D4 D5 D6
D4 D5
Pulsing stops because TE bit is set to 0.
D6
23. Serial Interface (UART2)
D7
D7
D8
P
SP
SP SP
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ST
ST
D0 D1
D0 D1