R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 280

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
19.2.3
Notes:
19.2.4
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0121h
Address 0122h
Symbol
Symbol
Symbol
Symbol
Bit
CCLR
Bit
IMIEA
IMIEB
IMIEC
IMIED
TCK0
TCK1
TCK2
OVIE
TOA
TOB
TOC
TOD
Timer RC Control Register 1 (TRCCR1)
Timer RC Interrupt Enable Register (TRCIER)
—
—
—
CCLR
OVIE
b7
b7
0
0
TRCIOA output level select bit
TRCIOB output level select bit
TRCIOC output level select bit
TRCIOD output level select bit
Count source select bit
TRC counter clear select bit
Input capture / compare match interrupt
enable bit A
Input capture / compare match interrupt
enable bit B
Input capture / compare match interrupt
enable bit C
Input capture / compare match interrupt
enable bit D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Overflow interrupt enable bit
TCK2
b6
b6
—
0
1
Bit Name
Bit Name
TCK1
b5
b5
—
0
1
(1)
TCK0
b4
b4
—
(1)
(1)
(1)
(1)
0
1
Function varies according to the operating mode
(function).
b6 b5 b4
0: Disable clear (free-running operation)
1: Clear TRC counter by input capture or by compare
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F
match in TRCGRA
IMIED
TOD
b3
b3
0
0
0: Disable interrupt (IMIA) by the IMFA bit
1: Enable interrupt (IMIA) by the IMFA bit
0: Disable interrupt (IMIB) by the IMFB bit
1: Enable interrupt (IMIB) by the IMFB bit
0: Disable interrupt (IMIC) by the IMFC bit
1: Enable interrupt (IMIC) by the IMFC bit
0: Disable interrupt (IMID) by the IMFD bit
1: Enable interrupt (IMID) by the IMFD bit
0: Disable interrupt (OVI) by the OVF bit
1: Enable interrupt (OVI) by the OVF bit
IMIEC
TOC
b2
b2
(2)
0
0
Function
IMIEB
TOB
Function
b1
b1
0
0
IMIEA
TOA
b0
b0
0
0
Page 249 of 715
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—