R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 181
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 11.4
11.3.5
11.3.6
Table 11.5
Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor
2, address break
Software, address match, single-step
Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an
interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt
response time includes the period from when an interrupt request is generated until the currently executing
instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence
(20 cycles, refer to (b) in Figure 11.4).
When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt
is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 11.5 is set in
the IPL.
Table 11.5 lists the IPL Value When Software or Special Interrupt is Acknowledged.
Interrupt request generation
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
IPL Value When Software or Special Interrupt is Acknowledged
Interrupt Response Time
Interrupt Source without Interrupt Priority Level
(a) The period from when an interrupt request is generated until the currently executing instruction is completed.
(b) 21 cycles for address match and single-step interrupts.
The length of time varies depending on the instruction being executed. The DIVX instruction requires
the longest time, 30 cycles (no wait states if the divisor is a register).
Instruction
(a)
Interrupt response time
Interrupt request acknowledgement
Interrupt sequence
20 cycles (b)
interrupt routine
Instruction in
Time
Value Set in IPL
Not changed
7
Page 150 of 715
11. Interrupts
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