R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 650

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
31.4.3
Notes:
1. To set the FMR13 bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between
2. To set this bit to 0, first write 1 and then 0 immediately. Disable interrupts and DTC activation between writing 1
3. This bit is set to 0 when the FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled).
FMR13 Bit (Lock Bit Disable Select Bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 01B5h
[Conditions for setting to 0]
The FMR13 bit is set to 0 when one of the following conditions is met.
[Condition for setting to 1]
Set to 1 by a program.
writing 0 and writing 1.
and writing 0.
When the FMR13 bit is set to 1 (lock bit disabled), the lock bit is disabled. When the FMR13 bit is set to 0, the
lock bit is enabled. Refer to 31.4.10 Data Protect Function for the details of the lock bit.
The FMR13 bit enables the lock bit function only and the lock bit data does not change. However, when a block
erase command is executed while the FMR13 bit is set to 1, the lock bit data set to 0 (locked) changes to 1 (not
locked) after erasure completes.
•
•
•
•
•
•
•
Symbol
Completion of the program command
Completion of the erase command
Generation of a command sequence error
Transition to erase-suspend
If the FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled).
If the FMSTP bit in the FMR0 register is set to 1 (flash memory stops).
If the CMDRST bit in the FMR0 register is set to 1 (erasure/writing stopped).
Symbol
FMR13 Lock bit disable select bit
FMR14 Data flash block A rewrite
FMR15 Data flash block B rewrite
FMR16 Data flash block C rewrite
FMR17 Data flash block D rewrite
Bit
Flash Memory Control Register 1 (FMR1)
—
—
—
FMR17
b7
0
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
disable bit
disable bit
disable bit
disable bit
FMR16
b6
0
(2, 3)
(2, 3)
(2, 3)
(2, 3)
Bit Name
FMR15
b5
0
(1)
FMR14
b4
0
0: Lock bit enabled
1: Lock bit disabled
0: Rewrite enabled (software command acceptable)
1: Rewrite disabled (software command not acceptable,
0: Rewrite enabled (software command acceptable)
1: Rewrite disabled (software command not acceptable,
0: Rewrite enabled (software command acceptable)
1: Rewrite disabled (software command not acceptable,
0: Rewrite enabled (software command acceptable)
1: Rewrite disabled (software command not acceptable,
no error occurred)
no error occurred)
no error occurred)
no error occurred)
FMR13
b3
0
b2
—
0
Function
b1
—
0
b0
—
0
31. Flash Memory
Page 619 of 715
R/W
R/W
R/W
R/W
R/W
R/W
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