R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 615
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Table 28.3
Start process time
A/D conversion
execution time
Between-execution process time
End process time
Table 28.3 shows the Number of Cycles for A/D Conversion Items. The A/D conversion time is defined as
follows.
The start process time varies depending on which φ AD is selected.
When 1 (A/D conversion starts) is written to the ADST bit in the ADCON0 register, an A/D conversion starts
after the start process time has elapsed. Reading the ADST bit before the A/D conversion returns 0 (A/D
conversion stops).
In the modes where an A/D conversion is performed on multiple pins or multiple times, the between-execution
process time is inserted between the A/D conversion execution time for one pin and the next A/D conversion
time.
In one-shot mode and single sweep mode, the ADST bit is set to 0 during the end process time and the last A/D
conversion result is stored in the ADi register.
•
•
In on-shot mode
Start process time + A/D conversion execution time + end process time
When two pins are selected in single sweep mode
Start process time + (A/D conversion execution time + between-execution process time + A/D conversion
execution time) + end process time
Number of Cycles for A/D Conversion Items
A/D Conversion Item
φ AD = fAD
φ AD = fAD divided by 2
φ AD = fAD divided by 4
φ AD = fAD divided by 8
Open-circuit detection disabled
Open-circuit detection enabled
1 or 2 fAD cycles
2 or 3 fAD cycles
3 or 4 fAD cycles
5 or 6 fAD cycles
2 or 3 fAD cycles
40 φ AD cycles
42 φ AD cycles
1 φ AD cycle
Number of Cycles
28. A/D Converter
Page 584 of 715
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