R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 21

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.
27.
25.6
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
27.1
27.2
27.3
27.4
25.5.3
25.5.4
26.2.1
26.2.2
26.2.3
26.2.4
26.2.5
26.2.6
26.2.7
26.2.8
26.2.9
26.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 533
26.2.11 Slave Address Register (SAR) .......................................................................................................... 534
26.2.12 IIC bus Shift Register (ICDRS) ........................................................................................................ 534
26.3.1
26.3.2
26.3.3
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.5.1
26.5.2
26.5.3
27.3.1
27.3.2
27.3.3
27.4.1
27.4.2
27.4.3
I
Hardware LIN .............................................................................................................................. 560
2
C bus Interface ......................................................................................................................... 523
Notes on Synchronous Serial Communication Unit .............................................................................. 522
Overview ............................................................................................................................................... 523
Registers ................................................................................................................................................ 526
Common Items for Multiple Modes ...................................................................................................... 535
I
Clock Synchronous Serial Mode ........................................................................................................... 550
Examples of Register Setting ................................................................................................................ 553
Noise Canceller ..................................................................................................................................... 557
Bit Synchronization Circuit ................................................................................................................... 558
Notes on I
Overview ............................................................................................................................................... 560
Input/Output Pins .................................................................................................................................. 561
Registers ................................................................................................................................................ 562
Function Description ............................................................................................................................. 564
2
C bus Interface Mode ......................................................................................................................... 539
Data Reception .................................................................................................................................. 519
SCS Pin Control and Arbitration ...................................................................................................... 521
Module Standby Control Register (MSTCR) ................................................................................... 526
SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 526
I/O Function Pin Select Register (PINSR) ....................................................................................... 527
IIC bus Transmit Data Register (ICDRT) ......................................................................................... 528
IIC bus Receive Data Register (ICDRR) .......................................................................................... 528
IIC bus Control Register 1 (ICCR1) ................................................................................................. 529
IIC bus Control Register 2 (ICCR2) ................................................................................................. 530
IIC bus Mode Register (ICMR) ........................................................................................................ 531
IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 532
Transfer Clock .................................................................................................................................. 535
SDA Pin Digital Delay Selection ...................................................................................................... 537
Interrupt Requests ............................................................................................................................. 538
I2C bus Format ................................................................................................................................. 539
Master Transmit Operation ............................................................................................................... 540
Master Receive Operation ................................................................................................................ 542
Slave Transmit Operation ................................................................................................................. 545
Slave Receive Operation ................................................................................................................... 548
Clock Synchronous Serial Format .................................................................................................... 550
Transmit Operation ........................................................................................................................... 551
Receive Operation ............................................................................................................................. 552
LIN Control Register 2 (LINCR2) .................................................................................................... 562
LIN Control Register (LINCR) ......................................................................................................... 563
LIN Status Register (LINST) ............................................................................................................ 563
Master Mode ..................................................................................................................................... 564
Slave Mode ....................................................................................................................................... 567
Bus Collision Detection Function ..................................................................................................... 571
2
C bus Interface .................................................................................................................... 559
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