R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 155

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
9.7
9.7.1
Table 9.3
−: Indicates that either 0 or 1 can be set.
High-speed
clock mode
Low-speed
clock mode
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
Standard operating mode is further separated into four modes.
In standard operating mode, the CPU and peripheral function clocks are supplied to operate the CPU and the
peripheral functions. Power consumption control is enabled by controlling the CPU clock frequency. The
higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the
more power consumption decreases. If unnecessary oscillator circuits stop, power consumption is further
reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. Allow sufficient wait time in a program until oscillation stabilizes before switching the clock.
Power Control
Modes
Standard Operating Mode
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Settings and Modes of Clock Associated Bits
Register
OCD2
OCD
0
0
0
0
0
−
−
−
−
−
1
1
1
1
1
1
1
1
1
1
CM17,
CM16
00b
01b
10b
00b
01b
10b
00b
01b
10b
00b
01b
10b
11b
11b
11b
11b
−
−
−
−
CM1 Register
CM14 CM13 CM07 CM06 CM05 CM04 CM03 FRA01 FRA00
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
CM0 Register
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
9. Clock Generation Circuit
−
−
−
−
−
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
Page 124 of 715
FRA0 Register
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
−
−
−
−
−