HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 226

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 7 Interrupt Controller (INTC)
Table 7.2
Name
Interrupt control register 0
Interrupt control register 1
Interrupt control register 2
Interrupt control register 3
PINT interrupt enable register
Interrupt priority level setting register A
Interrupt priority level setting register B
Interrupt priority level setting register C
Interrupt priority level setting register D
Interrupt priority level setting register E
Interrupt priority level setting register F
Interrupt priority level setting register G
Interrupt request register 0
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
Interrupt request register 4
Notes: 1. Initialized by a power-on or manual reset.
Rev.6.00 Mar. 27, 2009 Page 168 of 1036
REJ09B0254-0600
2. H'8000 when the NMI pin is at high level. H'0000 when the NMI pin is at low level.
3. When address translation by the MMU does not apply, the address in parentheses
should be used.
Register Configuration
IPRC
IPRD
IPRE
IPRF
IPRG
IRR1
IRR2
IRR3
IRR4
Abbr.
ICR0
ICR1
ICR2
ICR3
PINTER
IPRA
IPRB
IRR0
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial
Value *
*
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'00
H'00
H'00
H'00
H'00
2
1
Address
H'FFFFFEE0
H'04000010
(H'A4000010) *
H'04000012
(H'A4000012) *
H'04000228
(H'A4000228) *
H'04000014
(H'A4000014) *
H'FFFFFEE2
H'FFFFFEE4
H'04000016
(H'A4000016) *
H'04000018
(H'A4000018) *
H'0400001A
(H'A400001A) *
H'04000220
(H'A4000220) *
H'04000222
(H'A4000222) *
H'04000004
(H'A4000004) *
H'04000006
(H'A4000006) *
H'04000008
(H'A4000008) *
H'04000224
(H'A4000224) *
H'04000226
(H'A4000226) *
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Access
Size
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
16
16