HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 833
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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25.2.6
LDSARL sets the start address from which data is fetched by the LCDC for lower display of the
LCD panel. When a DSTN panel is used, this register specifies the fetch start address for the lower
side of the panel.
Bits 31 to 26—Reserved
Bits 25 to 0—Start Address for Lower Panel Display Data Fetch (SAL31 to SAL0): The start
address for data fetch of the display data must be set within the synchronous DRAM area of area
3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data corresponding to the lower panel
Note: The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the LCDC
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
handles these values as longword data, the values written to the lower two bits of each
register are always treated as 0. The lower two bits of each register are always read as 0.
For 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword
boundary (32 bits). (Data at the start of each line is always valid.) Data that exceeds the
longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. For 4, 8, 15,
16, or 32 bpp, set the registers so that the start of each line is aligned with the longword
boundary (32 bits).
LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
SAL15 SAL14 SAL13 SAL12 SAL11 SAL10 SAL9
R/W
R/W
31
15
—
0
0
R/W
R/W
30
14
—
0
0
R/W
R/W
29
13
—
0
0
R/W
R/W
28
12
—
0
0
R/W
R/W
27
11
—
1
0
R/W
R/W
26
10
—
1
0
SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16
R/W
R/W
25
0
9
0
SAL8
R/W
R/W
24
0
8
0
SAL7
Rev.6.00 Mar. 27, 2009 Page 775 of 1036
R/W
R/W
23
0
7
0
SAL6
R/W
R/W
22
0
6
0
SAL5
R/W
R/W
21
0
5
0
Section 25 LCD Controller
SAL4
R/W
R/W
20
0
4
0
SAL3
R/W
R/W
19
0
3
0
REJ09B0254-0600
SAL2
R/W
R/W
18
0
2
0
SAL1
R/W
R/W
17
0
1
0
SAL0
R/W
R/W
16
0
0
0
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