HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 681

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

This bit is effective when 1 is written to RXE bit of SICTR register. This bit is cleared when 1 is
written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this
bit.
Bit 2: TFUDR
0
1
Bit 1—Receive FIFO Under Run (RFUDR): Receive FIFO under run shows that SIRDR
register is read when receive FIFO is empty.
The data that has been read out from SIRDR is not guaranteed when this under run has occurred.
This bit is effective when 1 is written to RXE bit of SICTR register. This bit is cleared when 1 is
written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this
bit.
Bit 1: RFUDR
0
1
Bit 0—Receive FIFO Over Run (RFOVR): Receive FIFO over shows write action has occurred
to receive FIFO by SIOF, when receive FIFO is full. The received data disappears when receive
FIFO overrun occurs.
This bit is effective when 1 is written to TXE bit or RXE bit of SICTR register. This bit is cleared
when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is
allowed to this bit.
Bit 0: RFOVR
0
1
Description
Transmit FIFO under run does not occur
Transmit FIFO under run occurs
Description
Receive FIFO under run does not occur
Receive FIFO under run occurs
Description
Transmit over run does not generate
Transmit over run generate
Rev.6.00 Mar. 27, 2009 Page 623 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)