HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 860

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 25 LCD Controller
25.3.5
The timing controller register is used to run the controller in a way that matches the display
resolution of the LCD module. The display resolution is set up in the LCDC horizontal number
character number register, LCDC horizontal synchronization signal register, LCDC vertical line
displayed number register, LCDC vertical total line number register, and LCDC vertical
synchronization signal register. The LCD current-alternating period for an STN or DSTN display
is set by using the LCDC ac modulation signal toggle line number register. The initial values in
these registers are typical settings for VGA (640 × 480 dots) on an STN or DSTN display.
The clock to be used is set with the LCD input clock register. The LCD module frame rate is
determined by the display interval + retrace line interval (non-display interval) for one screen set
in a size related register and the frequency of the clock used.
This LCDC has a V
of each vertical retrace line period (to be exact, at the beginning of the line after the last line of the
display). This function is set up by using the LCDC interrupt control register.
25.3.6
An LCD module normally requires a specific sequence for processing to do with the cutoff of the
input power supply. Settings in the LCDC power management mode register, LCDC power supply
sequence period register, and LCDC control register, in conjunction with the LCD power-supply
control pins (VCPWC, VEPWC, and DON), are used to provide processing of power-supply
control sequences that suits the requirements of the LCD module.
Figures 25.4 to 25.7 are summary timing charts for power-supply control sequences and table 25.5
is a summary of available power-supply control sequence periods.
Rev.6.00 Mar. 27, 2009 Page 802 of 1036
REJ09B0254-0600
Timing Controller Register
Power Management Registers
sync
interrupt function so that it is possible to issue an interrupt at the beginning