HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 498

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
Table 14.10 Transfer Conditions and Register Settings for Transfer between External
Transfer Conditions
Transfer source: external memory
Value stored in address H'00400000
Value stored in address H'04500000
Transfer destination: On-chip SCIF TDR2
Number of transfers: 10
Transfer source address: incremented
Transfer destination address: fixed
Transfer request source: SCIF (TXI2)
Bus mode: cycle steal
Transfer unit: byte
Channel priority order: 0 > 1 > 2 > 3
When the indirect address is on, data stored in the address set in SAR is not used as transfer source
data. In the indirect address, after the value stored in the address set in SAR is read, the read value
is used as an address again, and the value stored in the address is read and stored in the address set
in DAR.
In the example shown in table 14.10, when an SCIF transfer request is generated, the DMAC reads
the value in address H'00400000 that is set in SAR3. Since the value H'00450000 is stored in the
address, the DMAC reads the value H'00450000. Next, the DMAC uses the read value as an
address again, and reads the value H'55 stored in that address. Then, the DMAC writes the value
H'55 to address H'04000156 that is set in DAR3; thus one indirect address transfer has completed.
In the indirect address, when data is read first from the address set in SAR3, the data transfer size
is always longword regardless of the settings of the TS0 and the TS1 bits that specify the transfer
data size. However, whether the transfer source address is fixed, incremented, or decremented is
specified with the SM0 and SM1 bits. Therefore, in this example, though the transfer data size is
specified as byte, the value in SAR3 is H'00400004 when one transfer ends. The write operation is
the same as that in the normal dual address transfer.
Rev.6.00 Mar. 27, 2009 Page 440 of 1036
REJ09B0254-0600
No interrupt request generated at end of transfer
Memory and SCIF Transmitter
—
DAR3
DMATCR3
CHCR3
Register
SAR3
—
DMAOR
Setting
H'00400000
H'00450000
H'55
H'04000156
H'0000000A
H'00011C01
H'0001