HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 52
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 3 Memory Management Unit (MMU)
Table 3.1
Table 3.2
Section 4 Exception Handling
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Section 5 Cache
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Section 6 X/Y Memory
Table 6.1
Section 7 Interrupt Controller (INTC)
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Section 8 User Break Controller
Table 8.1
Table 8.2
Section 9 Power-Down Modes and Software Reset
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Rev.6.00 Mar. 27, 2009 Page l of lvi
REJ09B0254-0600
Register Configuration ........................................................................................... 103
Access States Designated by D, C, and PR Bits..................................................... 110
Register Configuration ........................................................................................... 131
Exception Event Vectors ........................................................................................ 133
Exception Codes..................................................................................................... 136
Types of Reset........................................................................................................ 141
Cache Specifications .............................................................................................. 149
LRU and Way Replacement................................................................................... 151
Register Configuration ........................................................................................... 151
LRU and Way Replacement (when W2LOCK=1)................................................. 153
LRU and Way Replacement (when W3LOCK=1)................................................. 153
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) .................... 154
X/Y Memory Specifications................................................................................... 161
Pin Configuration ................................................................................................... 167
Register Configuration ........................................................................................... 168
IRL3 to IRL0 Pins and Interrupt Levels................................................................. 171
Interrupt Exception Handling Sources and Priority (IRQ Mode)........................... 174
Interrupt Exception Handling Sources and Priority (IRL Mode) ........................... 176
Interrupt Level and INTEVT Code ........................................................................ 178
Interrupt Request Sources and IPRA to IPRG........................................................ 179
Interrupt Response Time ........................................................................................ 200
Register Configuration ........................................................................................... 205
Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 223
Power-Down Modes............................................................................................... 234
Pin Configuration ................................................................................................... 235
Register Configuration ........................................................................................... 235
Register States in Standby Mode............................................................................ 244
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