HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 239
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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7.3.3
The ICR1 is a 16-bit register that specifies the detection mode to external interrupt input pins,
IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register, initialized to
H'4000 at power-on reset or manual reset, is not initialized in the standby mode.
Bit 15—Mask All Interrupts (MAI): Masks NMI interrupts in standby mode when set to 1. Also
selects whether or not all interrupt requests are masked when a low level is being input to the NMI
pin.
Bit 15: MAI
0
1
Bit 14—Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3 to IRQ0 pins are
used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3 to IRL0.
Bit 14: IRQLVL Description
0
1
Bit 13—BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit
of the SR register is 1.
Initial value:
Initial value:
Interrupt Control Register 1 (ICR1)
R/W:
R/W:
Bit:
Bit:
Description
All interrupt requests are not masked while NMI pin is receiving low-level input
All interrupt requests are masked while NMI pin is receiving low-level input
Used as four independent interrupt request pins IRQ3 to IRQ0
Used as encoded 15-level interrupt pins as IRL3 to IRL0
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
R/W
R/W
MAI
15
0
7
0
IRQLVL BLMSK
R/W
R/W
14
1
6
0
R/W
R/W
13
0
5
0
R/W
12
—
—
0
4
0
Rev.6.00 Mar. 27, 2009 Page 181 of 1036
IRQ51S IRQ50S IRQ41S IRQ40S
Section 7 Interrupt Controller (INTC)
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
REJ09B0254-0600
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
R/W
R/W
8
0
0
0
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