HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 685
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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20.2.11 Receive Data Register (SIRDR)
This register reads receive data of SIOF. The data from receive FIFO is stored in this register. This
register is initialized at power on reset, software reset, or transmit reset.
Bits 31 to 16—Receive Data for Left Channel (SIRDL15 to SIRDL0): These bits stores
received data from RXD_SIO as left channel data. The position of left channel side data are
assumed as the position what defined by RDLA bit of SIRDAR register.
These bits are effective when 1 is written to RDLE bit of SIRDAR register.
Bits 15 to 0—Receive Data for Right Channel (SIRDR15 to SIRDR0): These bits stores
received data from RXD_SIO as right channel data. The position of left channel side data are
assumed as the position what defined by RDRA bit of SIRDAR register.
These bits are effective when 1 is written to RDRE bit of SIRDAR register.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SIRDR
SIRDL
31
15
15
15
R
R
0
0
SIRDR
SIRDL
30
14
14
14
R
R
0
0
SIRDR
SIRDL
29
13
13
13
R
R
0
0
SIRDR
SIRDL
28
12
12
12
R
R
0
0
SIRDR
SIRDL
27
11
11
11
R
R
0
0
SIRDR
SIRDL
26
10
10
10
R
R
0
0
SIRDR
SIRDL
25
R
R
9
0
9
9
0
SIRDR
SIRDL
24
R
R
8
0
8
8
0
SIRDR
SIRDL
Rev.6.00 Mar. 27, 2009 Page 627 of 1036
23
R
R
7
0
7
7
0
SIRDR
SIRDL
22
R
R
6
0
6
6
0
SIRDR
SIRDL
21
R
R
5
0
5
5
0
Section 20 Serial IO (SIOF)
SIRDR
SIRDL
20
R
R
4
0
4
4
0
SIRDR
SIRDL
19
R
R
3
0
3
3
0
REJ09B0254-0600
SIRDR
SIRDL
18
R
R
2
0
2
2
0
SIRDR
SIRDL
17
R
R
1
0
1
1
0
SIRDR
SIRDL
16
R
R
0
0
0
0
0
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