HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 938
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 29 D/A Converter
29.1.3
Table 29.1 summarizes the D/A converter’s input and output pins.
Table 29.1 D/A Converter Pins
Pin Name
Analog power-supply pin
Analog ground pin
Analog output pin 0
Analog output pin 1
29.1.4
Table 29.2 summarizes the D/A converter’s registers.
Table 29.2 D/A Converter Registers
Name
D/A data register 0
D/A data register 1
D/A control register
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
Rev.6.00 Mar. 27, 2009 Page 880 of 1036
REJ09B0254-0600
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Lower 16 bits of the address
2. When address translation by the MMU does not apply, the address in parentheses
I/O Pins
Register Configuration
should be used.
Abbreviation R/W
DADR0
DADR1
DACR
Abbreviation
AVcc
AVss
DA0
DA1
R/W
R/W
R/W
I/O
Input
Input
Output
Output
Initial Value
H'00
H'00
H'1F
Function
Analog power supply and D/A converter
standard voltage
Analog ground
Analog output, channel 0
Analog output, channel 1
Address *
H'040000A0
(H'A40000A0) *
H'040000A2
(H'A40000A2) *
H'040000A4
(H'A40000A4) *
1
2
2
2
Access size
8
8
8
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