HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 668

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
Bit 5—Transmit or Receive Control Command Interrupt Mode (RCIM)
Bit 5: RCIM
0
1
20.2.2
This register sets the operate of baud rate generator. To set up this register, TRMD bit of SIMDR
register must be set 10 or 11.
This register is initialized in power on reset or software reset.
Note: * 0 must be written into this bit. The operation of this LSI is unpredictable when setting the
Bit 15—Master Clock Source Choice (MSSEL): Master clock means the clock that is input to
the baud rate generator.
Bit 15: MSSEL
0
1
Rev.6.00 Mar. 27, 2009 Page 610 of 1036
REJ09B0254-0600
Initial value:
Initial value:
value other than 0.
R/W:
R/W:
Clock Select Register (SISCR)
Bit:
Bit:
MSSEL
R/W
R*
15
—
0
7
0
Description
Set RCRDY bit of SISTR register when the contents of SIRCR register is
changed.
Set RCRDY bit of SISTR register when every control commands are received
and set to SIRCR register
Description
Use external clock source SIOMCLK input signal as master clock (Initial value)
Use peripheral clock (Pφ) as master clock
MSIMM
R/W
R*
14
—
0
6
0
R*
R*
13
—
—
0
5
0
BRPS4
R/W
R*
12
—
0
4
0
BRPS3
R/W
R*
11
—
0
3
0
BRPS2
BRDV2
R/W
R/W
10
0
2
0
BRDV1
BRPS1
R/W
R/W
9
0
1
0
(Initial value)
BRDV0
BRPS0
R/W
R/W
8
0
0
0