HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 722

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 21 Analog Front End Interface (AFEIF)
21.2.4
ASTR is the control register for AFEIF, and composed of ASTR1 and ASTR2. ASTR1 is mainly
used for transmit/receive FIFO interrupt control commands. ASTR2 is used for DAA interrupt
control commands. See section 21.3.1, Interrupt Timing for more detail about interrupt handling.
(1) AFEIF Status Register 1 (ASTR1)
ASTR1 is composed by interrupt status flags (4 bits) relating transmit/receive FIFO and mask
flags (4 bits) for transmit/receive FIFO interrupt signal. Status flag displays full/empty interrupt
status of transmit/receive FIFO and half size interrupt status for FIFO. FIFO empty (TFE) and
FIFO half size interrupt(THE) shows “1” as initial value, because transmit FIFO is empty after
power on reset. These interrupt flags are to be cleared with the data write / read action to FIFO
from CPU.
Each interrupt mask flag is able to prohibit interrupt generation of each interrupt that indicated in
interrupt status flag. Every mask bits are automatically set when TE or RE bit are modified to 1.
TFEM and THEM are 1 when TE = 0. RFFM and RHFM are “1” when RE = “0”. Each mask bit
are reset as 1.
Bits 15 to 12 and 7 to 4—Reserved
Bit 11—Tx FIFO Empty Interrupt Mask (TFEM)
Bit 11: TFEM
0
1
Rev.6.00 Mar. 27, 2009 Page 664 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
AFEIF Status Register 1 and 2 (ASTR1, ASTR2)
Bit:
Bit:
R/W
15
—
—
R
0
7
0
Description
TFE Interrupt enable
TFE interrupt masked
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
TFEM
R/W
TFE
11
R
1
3
1
RFFM
R/W
RFF
10
R
1
2
0
THEM
THE
R/W
R
9
1
1
1
(Initial value)
RHFM
RHF
R/W
R
8
1
0
0