HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 269

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

8.2.6
BDRB is a 32-bit read/write register. The control bits XYE and XYS in BBRB select a data bus
for break condition B. If the XYE is 0, then BDRB specifies the break data on LDB or IDB. If the
XYE is 1, then BDB 31 to 16 specifies the break data on XDB (bits 15 to 0) and BDB 15 to 0
specifies the break data on YDB (bits 15 to 0). However, you have to choose one of two data
buses for the break. A power-on reset initializes BDRB to H'00000000.
XYE = 0
XYE = 1
Initial value:
Initial value:
R/W: R/W
R/W: R/W
Bit:
Bit:
Break Data Register B (BDRB)
BDB
BDB
31
31
15
15
0
0
BDB
BDB
R/W
R/W
30
30
14
14
0
0
BDB31 to 16
XDB15 to 0 (XYS = 0)
L(I) DB31 to 16
BDB
BDB
R/W
R/W
29
29
13
13
0
0
BDB
BDB
R/W
R/W
28
28
12
12
0
0
BDB
BDB
R/W
R/W
27
27
11
11
0
0
BDB
BDB
R/W
R/W
26
26
10
10
0
0
BDB
BDB
R/W
R/W
25
25
0
9
9
0
BDB
BDB
R/W
R/W
24
24
0
8
8
0
Rev.6.00 Mar. 27, 2009 Page 211 of 1036
BDB
BDB
R/W
R/W
23
23
0
7
7
0
BDB15 to 0
L(I) DB15 to 0
YDB15 to 0 (XYS = 1)
BDB
BDB
R/W
R/W
22
22
0
6
6
0
Section 8 User Break Controller
BDB
BDB
R/W
R/W
21
21
0
5
5
0
BDB
BDB
R/W
R/W
20
20
0
4
4
0
BDB
BDB
R/W
R/W
19
19
0
3
3
0
REJ09B0254-0600
BDB
BDB
R/W
R/W
18
18
0
2
0
2
BDB
BDB
R/W
R/W
17
17
0
1
1
0
BDB
BDB
R/W
R/W
16
16
0
0
0
0