HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 298
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 9 Power-Down Modes and Software Reset
Bit 5— Module Stop 15 (MSTP15): Specifies halting the clock supply to the AFE interface
(AFE IF). When the MSTP15 bit is set to 1, the clock supply to the AFE interface is halted.
Bit 5: MSTP15
0
1
Bit 4— Module Stop 14 (MSTP14): Specifies halting the clock supply to the USB function
module (USBF). When the MSTP14 bit is set to 1, the clock supply to the USBF is halted.
Bit 4: MSTP14
0
1
Bit 3—Module Stop 13 (MSTP13): Specifies halting the clock supply to the USB host controller
(USBH). When the MSTP13 bit is set to 1, the clock supply to the USBH is halted.
Bit 3: MSTP13
0
1
Note: This bit should not be set to 1 when MSTP14 (bit 4) is 0.
Bit 2——Reserved: This bit is always read as 0. The write value should always as 0.
Bit 1— Module Stop 11 (MSTP11): Specifies halting the clock supply LCD Controller (LCDC).
When the MSTP11 bit is set to 1, the clock supply to the LCDC is halted.
Bit 1: MSTP11
0
1
Bit 0— Module Stop 10 (MSTP10): Specifies halting the clock supply to PC Card Controller
(PCC). When the MSTP10 bit is set to 1, the clock supply to the PCC is halted.
Bit 0: MSTP10
0
1
Rev.6.00 Mar. 27, 2009 Page 240 of 1036
REJ09B0254-0600
Description
AFE interface runs
Clock supply to AFE interface halted
Description
USBF runs
Clock supply to USBF halted
Description
USBH runs
Clock supply to USBH halted
Description
LCDC runs
Clock supply to LCDC halted
Description
PCC runs
Clock supply to PCC halted
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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