HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 674

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
20.2.6
This register sets the operating states of SIOF.
This register is initialized at power on reset or software reset.
Bits 13 to 10, and 7 to 2—Reserved
Bit 15—Serial Clock Output Enable (SCKE): This bit is effective in master mode. When 1 is
set to this bit, SIOF initializes baud rata generator, then starts, operation, and outputs the clock that
is generated by baud rate generator to SCK_SIO.
Bit 15: SCKE
0
1
Bit 14—Frame Synchronize Signal Output Enable (FSE): This bit is effective at master mode.
When 1 is set to this bit, SIOF initializes the frame counter, then starts operation.
Bit 14: FSE
0
1
Rev.6.00 Mar. 27, 2009 Page 616 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Serial Control Register (SICTR)
Bit:
Bit:
SCKE
R/W
15
—
R
0
7
0
Description
Disable output of SCK_SIO (outputs 0)
Enable output of SCK_SIO
Description
Disable output of SIOFSYNC (outputs 0)
Enable output of SIOFSYNC
FSE
R/W
14
—
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
11
—
—
R
R
0
3
0
10
—
—
R
R
0
2
0
TXRST
TXE
R/W
W
9
0
1
0
(Initial value)
(Initial value)
RXRST
RXE
R/W
W
8
0
0
0