HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 248
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 7 Interrupt Controller (INTC)
Bit 0: IRQ0R
0
1
7.3.8
The IRR1 is an 8-bit read-only register that indicates whether DMAC or interrupt requests are
generated. This register is initialized to H'00 at power-on reset or manual reset, but is not
initialized in standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request
is generated.
Bit 3: DEI3R
0
1
Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request
is generated.
Bit 2: DEI2R
0
1
Bit 1—DEI1 Interrupt Request (DEI1R): Indicates whether a DEI1 (DMAC) interrupt request
is generated.
Bit 1: DEI1R
0
1
Rev.6.00 Mar. 27, 2009 Page 190 of 1036
REJ09B0254-0600
Initial value:
Interrupt Request Register 1 (IRR1)
R/W:
Bit:
Description
An interrupt request is not input to IRQ0 pin
An interrupt request is input to IRQ0 pin
Description
A DEI3 interrupt request is not generated
A DEI3 interrupt request is generated
Description
A DEI2 interrupt request is not generated
A DEI2 interrupt request is generated
Description
A DEI1 interrupt request is not generated
A DEI1 interrupt request is generated
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
DEI3R
R
3
0
DEI2R
R
2
0
DEI1R
R
0
1
(Initial value)
(Initial value)
(Initial value)
(Initial value)
DEI0R
R
0
0
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